-- 8608-instructions.lua
-- This file contains the formal definitions for each instruction in the 8608 architecture.
-- It is used by generate-architecture.lua, alongside the definitions in 8608-definition.lua, to generate the following:
--   instructionList.txt, a human-readable list of all instructions.
--   8608.asm, a set of definitions for CustomAsm that allows it to assemble 8608 programs.
--   The microcode ROM data, which is built into the physical CPU to control it.

-- List of definitions for every instruction
-- Each instruction definition contains:
--   Mnemonic: The mnemonic used to generate the assembler definitions and instruction list.
--     This is what must literally appear in the assembly code in order to generate this instruction, other than immediate values.
--     "imm8" means an 8-bit value.
--     "imm16" means a 16-bit value.
--   Opcode: The machine code byte that represents this operation.
--     Used by the assembler generator to map mnemonics to opcodes.
--     Used by the microcode generator to place the instruction's data within the microcode ROM, which is addressed by opcode.
--   List of control signals: Specifies the control lines that will be activated by the microcode when the instruction is executed.
--     Instructions may take multiple clock cycles. To convey this, each clock cycle is represented by an independent list of microcode signals.
--     Under the hood, the microcode ROM uses a 10-bit address: 8 bits for the opcode, and 2 bits for the clock cycle.
--     Because of this, each opcode may only use up to 4 clock cycles.
--     If more are required, the least significant bit of the opcode can be set by a control line, incrementing the opcode.
--     This causes one instruction to use up multiple opcodes.
--     The need for this is determined automatically by the microcode generator: whenever an instruction specifies more than 4 lists of control signals.
--   Description: A brief description of the instruction. Used to generate the instruction list.
--   C Code: Used to generate an emulator (as part of a separate project).
-- Categories can be specified. These serve only to organize the instruction list.
--   The category letter determines what letter will be used to represent the instructions in the opcode map, located at the bottom of the instruction list.
local instructions = {
	{ category = "Control", catlet="C" },
	{ mnem="RST"      , opcode=0x41, {"clearRegs","load16FC1","instrSub1"},{"load16FC2","instrSub2"},{                                                      "jmpAbsUT"}, desc="Clear all registers and flags, load the Program Counter from memory addresses $FFFC-$FFFD, and execute the code at the address given by those bytes"                , ccode={"cpu.a=0; cpu.b=0; cpu.c=0; cpu.u=0; cpu.t=0; cpu.p=0; cpu.q=0; cpu.s=0; cpu.v=0; cpu.i=0; cpu.cf=0; cpu.nz=0; cpu.rfg=1; cpu.ien=0; cpu.irq=0; cpu.ifg=0; cpu.u=readmemory(0xFFFC);","cpu.t=readmemory(0xFFFD);","jmpabsut;"} },
	{ mnem="INT"      , opcode=0x01, {            "load16FE1","instrSub1"},{"load16FE2","instrSub2"},{"intFlgVal","intFlgClk","irqFlgClk","saveIV",         "jmpAbsUT"},                                                                                                                                                                             ccode={"                                                                                                                                    cpu.irq=0; cpu.ifg=1; cpu.u=readmemory(0xFFFE);","cpu.t=readmemory(0xFFFF);","cpu.v=(cpu.i-1)%65536; jmpabsut;"} },
	{ mnem="BRK"      , opcode=0x00, {            "load16FE1","instrSub1"},{"load16FE2","instrSub2"},{"intFlgVal","intFlgClk"            ,"saveIV","adwInc","jmpAbsUT"}, desc="Trigger an interrupt from software, saving the current Program Counter in the V register and jumping to the Interrupt Vector stored at memory addresses $FFFE-$FFFF", ccode={"                                                                                                                                               cpu.ifg=1; cpu.u=readmemory(0xFFFE);","cpu.t=readmemory(0xFFFF);","cpu.v=(cpu.i  )%65536; jmpabsut;"} },
	{ mnem="RTI"      , opcode=0x40, {"adwInc","intFlgClk","jmpAbsV"}, desc="Return from an interrupt, resuming normal execution where it left off when the interrupt occurred", ccode={"cpu.ifg=0; int t=cpu.i; cpu.i=cpu.v; cpu.v=t; lni;"} },
	{ mnem="NOP"      , opcode=0xEA, {"instrNext"}, desc="Do nothing", ccode={"lni;"}, },
	{ mnem="CLI"      , opcode=0x58, {"instrNext"}, desc="Enable interrupts to be triggered by external hardware", ccode={"cpu.ien=1; lni;"}, }, -- todo
	{ mnem="SEI"      , opcode=0x78, {"instrNext"}, desc="Disable interrupts being triggered by external hardware", ccode={"cpu.ien=0; lni;"}, }, -- todo
	{ mnem="HLT"      , opcode=0x18, {"runFlgClk","instrNext"}, desc="Clear the Run Flag, preventing the CPU from running until an interrupt is triggered", ccode={"cpu.rfg=0; lni;"} },
	{ mnem="RUN"      , opcode=0x38, {"runFlgClk","runFlgVal","instrNext"}, desc ="Set the Run Flag, allowing the CPU to run once the current interrupt finishes", ccode={"cpu.rfg=1; lni;"} },
	
--	{ category = "16-bit Increment/Decrement", catlet="I" },
--	{ mnem="INX"      , opcode=0x11, {"adwlP","adwInc","adwSaveP","instrNext"}, desc="Increment the 16-bit X register", ccode={"cpu.p++; lni;"} },
--	{ mnem="DEX"      , opcode=0x31, {"adwlP","adwrm1","adwSaveP","instrNext"}, desc="Decrement the 16-bit X register", ccode={"cpu.p--; lni;"} },
--	{ mnem="INY"      , opcode=0x51, {"adwlQ","adwInc","adwSaveQ","instrNext"}, desc="Increment the 16-bit Y register", ccode={"cpu.q++; lni;"} },
--	{ mnem="DEY"      , opcode=0x71, {"adwlQ","adwrm1","adwSaveQ","instrNext"}, desc="Decrement the 16-bit Y register", ccode={"cpu.q--; lni;"} },
	
	{ category = "8-bit Unary Arithmetic", catlet="U" },
	{ mnem="INC A"    , opcode=0xF6,                                                            {"aluA","alur1" ,"aluOpAdd" ,"instrNext"}, desc="Increment the A register, %flags"            , ccode={"addf(cpu.a, 1    ); lni;"} },
	{ mnem="DEC A"    , opcode=0xD6,                                                            {"aluA","alurm1","aluOpAdd" ,"instrNext"}, desc="Decrement the A register, %flags"            , ccode={"addf(cpu.a,-1    ); lni;"} },
	{ mnem="ICC A"    , opcode=0x57,                                                            {"aluA",         "aluOpAddC","instrNext"}, desc="Add the Carry Flag to the A register, %flags", ccode={"addf(cpu.a,cpu.cf); lni;"} },
	{ mnem="INC B"    , opcode=0xFE,                                                            {"aluB","alur1" ,"aluOpAdd" ,"instrNext"}, desc="Increment the B register, %flags"            , ccode={"addf(cpu.b, 1    ); lni;"} },
	{ mnem="DEC B"    , opcode=0xDE,                                                            {"aluB","alurm1","aluOpAdd" ,"instrNext"}, desc="Decrement the B register, %flags"            , ccode={"addf(cpu.b,-1    ); lni;"} },
	{ mnem="ICC B"    , opcode=0x5F,                                                            {"aluB",         "aluOpAddC","instrNext"}, desc="Add the Carry Flag to the B register, %flags", ccode={"addf(cpu.b,cpu.cf); lni;"} },
	{ mnem="INC C"    , opcode=0xFA,                                                            {"aluC","alur1" ,"aluOpAdd" ,"instrNext"}, desc="Increment the C register, %flags"            , ccode={"addf(cpu.c, 1    ); lni;"} },
	{ mnem="DEC C"    , opcode=0xDA,                                                            {"aluC","alurm1","aluOpAdd" ,"instrNext"}, desc="Decrement the C register, %flags"            , ccode={"addf(cpu.c,-1    ); lni;"} },
	{ mnem="ICC C"    , opcode=0x5B,                                                            {"aluC",         "aluOpAddC","instrNext"}, desc="Add the Carry Flag to the C register, %flags", ccode={"addf(cpu.c,cpu.cf); lni;"} },
--	{ mnem="TST A"    , opcode=0x  ,                                                            {"alulA",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to A-0", ccode={"tst(cpu.a); lni;"} },
--	{ mnem="TST B"    , opcode=0x  ,                                                            {"alulB",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to B-0", ccode={"tst(cpu.b); lni;"} },
--	{ mnem="TST C"    , opcode=0x  ,                                                            {"alulC",        "aluOpCmp" ,"instrNext"}, desc="Set flags according to C-0", ccode={"tst(cpu.c); lni;"} },
	{ mnem="INC zpg"  , opcode=0xE6, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alur1" ,"aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="Increment the value at %zpg, %flags"             , ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u, 1    );","storestackrelu; instrloadpre"} },
	{ mnem="DEC zpg"  , opcode=0xC6, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU","alurm1","aluOpAdd" ,"instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="Decrement the value at %zpg, %flags"             , ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u,-1    );","storestackrelu; instrloadpre"} },
	{ mnem="ICC zpg"  , opcode=0x47, {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"aluU",         "aluOpAddC","instrSub3","instrPreload"}, {"storeStackRelU","instrNextPre"}, desc="Add the Carrry Flag to the value at %zpg, %flags", ccode={"loadimmedt","loadstackrelu","instrpreload; addf(cpu.u,cpu.cf);","storestackrelu; instrloadpre"} },
--	{ mnem="TST zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelU","instrSub2"}, {"alulU",        "aluOpCmp" ,"instrNext"},                                                   desc="Set flags according to *(S+imm8)-0", ccode={"loadimmedt","loadstackrelu","tst(cpu.u); lni;"} },
	
	{ category = "8-bit Arithmetic and Logic", catlet="A" },
	{ mnem="ADD #"    , opcode=0x6B, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="Add %imm8 to %A, %flags"                                 , ccode={"loadimmedt","addf(cpu.a,cpu.t); lni;"} },
--	{ mnem="ADB #"    , opcode=0x  , {"loadImmedT","instrSub1"},                                {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc=""                                                        , ccode={"loadimmedt","addf(cpu.b,cpu.t); lni;"} },
--	{ mnem="ADC #"    , opcode=0x  , {"loadImmedT","instrSub1"},                                {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc=""                                                        , ccode={"loadimmedt","addf(cpu.c,cpu.t); lni;"} },
	{ mnem="SUB #"    , opcode=0xEB, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="Subtract %imm8 from %A, %flags"                          , ccode={"loadimmedt","subf(cpu.a,cpu.t); lni;"} },
	{ mnem="ADC #"    , opcode=0x69, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAddC","instrNext"}, desc="Add %imm8 plus the Carry Flag to %A, %flags"             , ccode={"loadimmedt","addf(cpu.a,cpu.t+cpu.cf); lni;"} },
	{ mnem="SBC #"    , opcode=0xE9, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSubC","instrNext"}, desc="Subtract %imm8 from %A including the Carry Flag, %flags" , ccode={"loadimmedt","addf(cpu.a,~cpu.t+cpu.cf); lni;"} },
	{ mnem="CMP #"    , opcode=0xC9, {"loadImmedT","instrSub1"},                                {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="%cmp %imm8 from %A"                                      , ccode={"loadimmedt","cmpf(cpu.a,cpu.t); lni;"} },
	{ mnem="AND #"    , opcode=0x29, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="Bitwise AND %A with %imm8, %zflag"                       , ccode={"loadimmedt","cpu.a&=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="ORA #"    , opcode=0x09, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="Bitwise OR %A with %imm8, %zflag"                        , ccode={"loadimmedt","cpu.a|=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="EOR #"    , opcode=0x49, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="Bitwise Exclusive OR %A with %imm8, %zflag"              , ccode={"loadimmedt","cpu.a^=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="ASL #"    , opcode=0x15, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="Bit-shift %A left by a given number of bits, %zflag"     , ccode={"loadimmedt","cpu.a<<=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="LSR #"    , opcode=0x55, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="Bit-shift %A right by a given number of bits, %zflag"    , ccode={"loadimmedt","cpu.a>>=cpu.t; setzf(cpu.a); lni;"} },
	{ mnem="ROL #"    , opcode=0x35, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="Bit-rotate %A left by a given number of bits, %zflag"    , ccode={"loadimmedt","cpu.a=rol(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
	{ mnem="ROR #"    , opcode=0x75, {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="Bit-rotate %A right by a given number of bits, %zflag"   , ccode={"loadimmedt","cpu.a=ror(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
--	{ mnem="ASR #"    , opcode=0x  , {"loadImmedT","instrSub1"},                                {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=imm8, set zero flag"                                , ccode={"loadimmedt","cpu.a=sra(cpu.a,cpu.t); setzf(cpu.a); lni;"} },
	{ mnem="ADD zpg"  , opcode=0x67, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAdd" ,"instrNext"}, desc="Add %zpgIn to %A, %flags"                                , ccode={"loadimmedt","loadstackrelu","addf(cpu.a,cpu.u); lni;"} },
--	{ mnem="adb zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpAdd" ,"instrNext"}, desc="B+=*(S+imm8), set flags"                                 , ccode={"loadimmedt","loadstackrelu","addf(cpu.b,cpu.u); lni;"} },
--	{ mnem="adc zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpAdd" ,"instrNext"}, desc="C+=*(S+imm8), set flags"                                 , ccode={"loadimmedt","loadstackrelu","addf(cpu.c,cpu.u); lni;"} },
	{ mnem="SUB zpg"  , opcode=0xE7, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSub" ,"instrNext"}, desc="Subtract %zpgIn from %A, %flags"                         , ccode={"loadimmedt","loadstackrelu","subf(cpu.a,cpu.u); lni;"} },
--	{ mnem="sbb zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluB", "alurT","aluOpSub" ,"instrNext"}, desc="B-=*(S+imm8), set flags"                                 , ccode={"loadimmedt","loadstackrelu","subf(cpu.b,cpu.u); lni;"} },
--	{ mnem="sbc zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluC", "alurT","aluOpSub" ,"instrNext"}, desc="C-=*(S+imm8), set flags"                                 , ccode={"loadimmedt","loadstackrelu","subf(cpu.c,cpu.u); lni;"} },
	{ mnem="ADC zpg"  , opcode=0x65, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAddC","instrNext"}, desc="Add %zpgIn plus the Carry Flag to %A, %flags"            , ccode={"loadimmedt","loadstackrelu","addf(cpu.a,cpu.u+cpu.cf); lni;"} },
	{ mnem="SBC zpg"  , opcode=0xE5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSubC","instrNext"}, desc="Subtract %zpgIn from %A including the Carry Flag, %flags", ccode={"loadimmedt","loadstackrelu","addf(cpu.a,~cpu.u+cpu.cf); lni;"} },
	{ mnem="CMP zpg"  , opcode=0xC5, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"alulA","alurT","aluOpSub" ,"instrNext"}, desc="%cmp %zpgIn from %A"                                     , ccode={"loadimmedt","loadstackrelu","cmpf(cpu.a,cpu.u); lni;"} },
	{ mnem="AND zpg"  , opcode=0x25, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpAnd" ,"instrNext"}, desc="Bitwise AND %A with %zpgIn, %flags"                      , ccode={"loadimmedt","loadstackrelu","cpu.a&=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="ORA zpg"  , opcode=0x05, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpIor" ,"instrNext"}, desc="Bitwise OR %A with %zpgIn, %flags"                       , ccode={"loadimmedt","loadstackrelu","cpu.a|=cpu.u; setzf(cpu.a); lni;"} },
	{ mnem="EOR zpg"  , opcode=0x45, {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpXor" ,"instrNext"}, desc="Bitwise Exclusive OR %A with %zpgIn, %flags"             , ccode={"loadimmedt","loadstackrelu","cpu.a^=cpu.u; setzf(cpu.a); lni;"} },
--	{ mnem="ASL zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShl" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag"                            , ccode={"loadimmedt","loadstackrelu","cpu.a<<=cpu.u; setzf(cpu.a); lni;"} },
--	{ mnem="LSR zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpShr" ,"instrNext"}, desc="A<<=*(S+imm8), set zero flag"                            , ccode={"loadimmedt","loadstackrelu","cpu.a>>=cpu.u; setzf(cpu.a); lni;"} },
--	{ mnem="ROL zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRol" ,"instrNext"}, desc="A<<<=*(S+imm8), set zero flag"                           , ccode={"loadimmedt","loadstackrelu","cpu.a=rol(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
--	{ mnem="ROR zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpRor" ,"instrNext"}, desc="A>>>=*(S+imm8), set zero flag"                           , ccode={"loadimmedt","loadstackrelu","cpu.a=ror(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
--	{ mnem="ASR zpg"  , opcode=0x  , {"loadImmedT","instrSub1"}, {"loadStackRelT","instrSub2"}, {"aluA", "alurT","aluOpSra" ,"instrNext"}, desc="A>>a=*(S+imm8), set zero flag"                           , ccode={"loadimmedt","loadstackrelu","cpu.a=sra(cpu.a,cpu.u); setzf(cpu.a); lni;"} },
	{ mnem="ADD B"    , opcode=0x7F,                                                            {"aluA", "alurB","aluOpAdd" ,"instrNext"}, desc="Add %B to %A, %flags"                                    , ccode={"addf(cpu.a,cpu.b); lni;"} },
--	{ mnem="adc B"    , opcode=0x  ,                                                            {"aluC", "alurB","aluOpAdd" ,"instrNext"}, desc="C+=B, set flags"                                         , ccode={"addf(cpu.c,cpu.b); lni;"} },
	{ mnem="SUB B"    , opcode=0xFF,                                                            {"aluA", "alurB","aluOpSub" ,"instrNext"}, desc="Subtract %B from %A, %flags"                             , ccode={"subf(cpu.a,cpu.b); lni;"} },
--	{ mnem="sbc B"    , opcode=0x  ,                                                            {"aluC", "alurB","aluOpSub" ,"instrNext"}, desc="C-=B, set flags"                                         , ccode={"subf(cpu.c,cpu.b); lni;"} },
	{ mnem="ADC B"    , opcode=0x7D,                                                            {"aluA", "alurB","aluOpAddC","instrNext"}, desc="Add %B plus the Carry Flag to %A, %flags"                , ccode={"addf(cpu.a,cpu.b+cpu.cf); lni;"} },
	{ mnem="SBC B"    , opcode=0xFD,                                                            {"aluA", "alurB","aluOpSubC","instrNext"}, desc="Subtract %B form %A including the Carry Flag, %flags"    , ccode={"addf(cpu.a,-cpu.b+cpu.cf); lni;"} },
	{ mnem="CMP B"    , opcode=0xDD,                                                            {"alulA","alurB","aluOpSub" ,"instrNext"}, desc="%cmp %B from %A"                                         , ccode={"cmpf(cpu.a,cpu.b); lni;"} },
	{ mnem="AND B"    , opcode=0x3D,                                                            {"aluA", "alurB","aluOpAnd" ,"instrNext"}, desc="Bitwise AND %A with %B, %flags"                          , ccode={"cpu.a&=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="ORA B"    , opcode=0x1D,                                                            {"aluA", "alurB","aluOpIor" ,"instrNext"}, desc="Bitwise OR %A with %B, %flags"                           , ccode={"cpu.a|=cpu.b; setzf(cpu.a); lni;"} },
	{ mnem="EOR B"    , opcode=0x5D,                                                            {"aluA", "alurB","aluOpXor" ,"instrNext"}, desc="Bitwise Exclusive OR %A with %B, %flags"                 , ccode={"cpu.a^=cpu.b; setzf(cpu.a); lni;"} },
--	{ mnem="ASL B"    , opcode=0x  ,                                                            {"aluA", "alurB","aluOpShl" ,"instrNext"}, desc="A<<=B, set zero flag"                                    , ccode={"cpu.a<<=cpu.b; setzf(cpu.a); lni;"} },
--	{ mnem="LSR B"    , opcode=0x  ,                                                            {"aluA", "alurB","aluOpShr" ,"instrNext"}, desc="A>>=B, set zero flag"                                    , ccode={"cpu.a>>=cpu.b; setzf(cpu.a); lni;"} },
--	{ mnem="ROL B"    , opcode=0x  ,                                                            {"aluA", "alurB","aluOpRol" ,"instrNext"}, desc="A<<<=B, set zero flag"                                   , ccode={"cpu.a=rol(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
--	{ mnem="ROR B"    , opcode=0x  ,                                                            {"aluA", "alurB","aluOpRor" ,"instrNext"}, desc="A>>>=B, set zero flag"                                   , ccode={"cpu.a=ror(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
--	{ mnem="ASR B"    , opcode=0x  ,                                                            {"aluA", "alurB","aluOpSra" ,"instrNext"}, desc="A>>a=B, set zero flag"                                   , ccode={"cpu.a=sra(cpu.a,cpu.b); setzf(cpu.a); lni;"} },
	{ mnem="ADD C"    , opcode=0x7B,                                                            {"aluA", "alurC","aluOpAdd" ,"instrNext"}, desc="Add %C to %A, %flags"                                    , ccode={"addf(cpu.a,cpu.c); lni;"} },
--	{ mnem="adb C"    , opcode=0x  ,                                                            {"aluB", "alurC","aluOpAdd" ,"instrNext"}, desc="B+=C, set flags"                                         , ccode={"addf(cpu.b,cpu.c); lni;"} },
	{ mnem="SUB C"    , opcode=0xFB,                                                            {"aluA", "alurC","aluOpSub" ,"instrNext"}, desc="Subtract %C from %A, %flags"                             , ccode={"subf(cpu.a,cpu.c); lni;"} },
--	{ mnem="sbb C"    , opcode=0x  ,                                                            {"aluB", "alurC","aluOpSub" ,"instrNext"}, desc="B-=C, set flags"                                         , ccode={"subf(cpu.b,cpu.c); lni;"} },
	{ mnem="ADC C"    , opcode=0x79,                                                            {"aluA", "alurC","aluOpAddC","instrNext"}, desc="Add %C plus the Carry Flag to %A, %flags"                , ccode={"addf(cpu.a,cpu.c+cpu.cf); lni;"} },
	{ mnem="SBC C"    , opcode=0xF9,                                                            {"aluA", "alurC","aluOpSubC","instrNext"}, desc="Subtract %C form %A including the Carry Flag, %flags"    , ccode={"addf(cpu.a,~cpu.c+cpu.cf); lni;"} },
	{ mnem="CMP C"    , opcode=0xD9,                                                            {"alulA","alurC","aluOpSub" ,"instrNext"}, desc="%cmp %C from %A"                                         , ccode={"cmpf(cpu.a,cpu.c); lni;"} },
	{ mnem="AND C"    , opcode=0x39,                                                            {"aluA", "alurC","aluOpAnd" ,"instrNext"}, desc="Bitwise AND %A with %C, %flags"                          , ccode={"cpu.a&=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="ORA C"    , opcode=0x19,                                                            {"aluA", "alurC","aluOpIor" ,"instrNext"}, desc="Bitwise OR %A with %C, %flags"                           , ccode={"cpu.a|=cpu.c; setzf(cpu.a); lni;"} },
	{ mnem="EOR C"    , opcode=0x59,                                                            {"aluA", "alurC","aluOpXor" ,"instrNext"}, desc="Bitwise Exclusive OR %A with %C, %flags"                 , ccode={"cpu.a^=cpu.c; setzf(cpu.a); lni;"} },
--	{ mnem="ASL C"    , opcode=0x  ,                                                            {"aluA", "alurC","aluOpShl" ,"instrNext"}, desc="A<<=C, set zero flag"                                    , ccode={"cpu.a<<=cpu.c; setzf(cpu.a); lni;"} },
--	{ mnem="LSR C"    , opcode=0x  ,                                                            {"aluA", "alurC","aluOpShr" ,"instrNext"}, desc="A>>=C, set zero flag"                                    , ccode={"cpu.a>>=cpu.c; setzf(cpu.a); lni;"} },
--	{ mnem="ROL C"    , opcode=0x  ,                                                            {"aluA", "alurC","aluOpRol" ,"instrNext"}, desc="A<<<=C, set zero flag"                                   , ccode={"cpu.a=rol(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
--	{ mnem="ROR C"    , opcode=0x  ,                                                            {"aluA", "alurC","aluOpRor" ,"instrNext"}, desc="A>>>=C, set zero flag"                                   , ccode={"cpu.a=ror(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
--	{ mnem="ASR C"    , opcode=0x  ,                                                            {"aluA", "alurC","aluOpSra" ,"instrNext"}, desc="A>>a=C, set zero flag"                                   , ccode={"cpu.a=sra(cpu.a,cpu.c); setzf(cpu.a); lni;"} },
--	{ mnem="adb a"    , opcode=0x  ,                                                            {"aluB", "alurA","aluOpAdd" ,"instrNext"}, desc="B+=A, set flags"                                         , ccode={"addf(cpu.b,cpu.a); lni;"} },
--	{ mnem="sbb a"    , opcode=0x  ,                                                            {"aluB", "alurA","aluOpSub" ,"instrNext"}, desc="B-=A, set flags"                                         , ccode={"subf(cpu.b,cpu.a); lni;"} },
--	{ mnem="adc a"    , opcode=0x  ,                                                            {"aluC", "alurA","aluOpAdd" ,"instrNext"}, desc="C+=A, set flags"                                         , ccode={"addf(cpu.c,cpu.a); lni;"} },
--	{ mnem="sbc a"    , opcode=0x  ,                                                            {"aluC", "alurA","aluOpSub" ,"instrNext"}, desc="C-=A, set flags"                                         , ccode={"subf(cpu.c,cpu.a); lni;"} },
	
	{ category = "Conditional Branches", catlet="B"},
	{ mnem="BNE rel"  , opcode=0xD0, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0NZ"              }, {}, {"instrNext"}, {"jmpRelT"}, desc="%if not 0, %brel; %brelc"        , ccode={"loadimmedt","if( cpu.nz               ) { jmprelt } else { lni }"} },
	{ mnem="BEQ rel"  , opcode=0xF0, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0Z"               }, {}, {"instrNext"}, {"jmpRelT"}, desc="%if 0, %brel; %brelc"            , ccode={"loadimmedt","if(!cpu.nz               ) { jmprelt } else { lni }"} },
	{ mnem="BLT rel"  , opcode=0x90, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0NC"              }, {}, {"instrNext"}, {"jmpRelT"}, desc="%if negative, %brel; %brelc"     , ccode={"loadimmedt","if(!cpu.cf               ) { jmprelt } else { lni }"} },
	{ mnem="BGE rel"  , opcode=0xB0, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0C"               }, {}, {"instrNext"}, {"jmpRelT"}, desc="%if positive or 0, %brel; %brelc", ccode={"loadimmedt","if( cpu.cf               ) { jmprelt } else { lni }"} },
	{ mnem="BGT rel"  , opcode=0x30, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0NC","instrNext0Z"}, {}, {"jmpRelT"}, {"instrNext"}, desc="%if positive, %brel; %brelc"     , ccode={"loadimmedt","if(  cpu.nz &&    cpu.cf ) { jmprelt } else { lni }"} },
	{ mnem="BLE rel"  , opcode=0x10, ncycles=2, {"loadImmedT","instrSub23Cond","instrNext0NC","instrNext0Z"}, {}, {"instrNext"}, {"jmpRelT"}, desc="%if negative or 0, %brel; %brelc", ccode={"loadimmedt","if((!cpu.nz) || (!cpu.cf)) { jmprelt } else { lni }"} },
	{ mnem="BRA rel"  , opcode=0x98,            {"loadImmedT",                                  "instrSub1"},                    {"jmpRelT"}, desc="%brel"                           , ccode={"loadimmedt",                             "jmprelt"               } },
	
	{ category = "16-bit Arithmetic", catlet = "X"},
	{ mnem="ADX #"    , opcode=0xE8,                            {"loadImmedT","instrSub1"}, {"adwP","adwrTX","instrNext"}, desc="Add %imm8 to the 16-bit X register"                                   , ccode={             "loadimmedt","cpu.p=(cpu.p+signed8(cpu.t))%65536; lni;"} },
	{ mnem="ADY #"    , opcode=0xC8,                            {"loadImmedT","instrSub1"}, {"adwQ","adwrTX","instrNext"}, desc="Add %imm8 to the 16-bit Y register"                                   , ccode={             "loadimmedt","cpu.q=(cpu.q+signed8(cpu.t))%65536; lni;"} },
--	{ mnem="ADS #"    , opcode=0x  ,                            {"loadImmedT","instrSub1"}, {"adwS","adwrTX","instrNext"}, desc="S+=imm8 signed"                                                       , ccode={             "loadimmedt","cpu.s=(cpu.s+signed8(cpu.t))%65536; lni;"} },
	{ mnem="ADX ##"   , opcode=0x8A, {"loadImm161","instrSub1"},{"loadImm162","instrSub2"}, {"adwP","adwrUT","instrNext"}, desc="Add %imm16 to the 16-bit X register"                                  , ccode={"loadimm161","loadimm162","cpu.p=(cpu.p+wordut        )%65536; lni;"} },
	{ mnem="ADY ##"   , opcode=0x88, {"loadImm161","instrSub1"},{"loadImm162","instrSub2"}, {"adwQ","adwrUT","instrNext"}, desc="Add %imm16 to the 16-bit Y register"                                  , ccode={"loadimm161","loadimm162","cpu.q=(cpu.p+wordut        )%65536; lni;"} },
	{ mnem="ADX A"    , opcode=0xFC,                                                        {"adwP","adwrAX","instrNext"}, desc="Add the 8-bit signed value in the A register to the 16-bit X register", ccode={                          "cpu.p=(cpu.p+signed8(cpu.a))%65536; lni;"} },
	{ mnem="ADY A"    , opcode=0xDC,                                                        {"adwQ","adwrAX","instrNext"}, desc="Add the 8-bit signed value in the A register to the 16-bit Y register", ccode={                          "cpu.q=(cpu.p+signed8(cpu.a))%65536; lni;"} },
--	{ mnem="ADS A"    , opcode=0x  ,                                                        {"adwS","adwrAX","instrNext"}, desc="S+=B signed", ccode={"cpu.s+=signed8(cpu.b); lni;"} },
	
	{ category = "Jumps" , catlet="J" },
	{ mnem="JMP abs"  , opcode=0xCC, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"},                                                                                                                                                    {"jmpAbsUT"              }, desc="Jump - Set the Program Counter to %imm16, executing the code at that address"                                                          , ccode={"loadimm161","loadimm162",                                                                                                                         "jmpabsut"            } },
--	{ mnem="jsy abs"  , opcode=0x  , {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"},                                                                                                                                                    {"jmpAbsUT","saveRetAddr"}, desc="I=imm16, Q=I"                                                                                                                          , ccode={"loadimm161","loadimm162",                                                                                                                         "jmpabsut saveretaddr"} },
	{ mnem="JSR abs"  , opcode=0x20, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushRetAddr1","instrSub3"}, {"pushRetAddr2","instrSub4"},                                                                                        {"jmpAbsUT"              }, desc="Jump to Subroutine - Save the Program Counter on the Stack, then set it to %imm16, executing the code at that address"                 , ccode={"loadimm161","loadimm162","pushretaddr1","pushretaddr2",                                                                                           "jmpabsut"            } }, -- 0x21
	{ mnem="JMP [ind]", opcode=0x6C, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"},                                                             {"load161","adrrUT",         "adrSaveI","instrSub3"}, {"load162","adrlI","instrSub4"}, {"jmpAbsUT"              }, desc="Load a subroutine pointer from memory at a given 16-bit address, then jump to that subroutine, saving the return address on the stack.", ccode={"loadimm161","loadimm162",                              "cpu.i=(wordut+cpu.a)%65536;cpu.u=readmemory(cpu.i);","cpu.t=readmemory((cpu.i+1)%65536);","jmpabsut"            } }, -- 0x6D
	{ mnem="JSR [ind]", opcode=0x2C, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushRetAddr1","instrSub3"}, {"pushRetAddr2","instrSub4"}, {"load161","adrrUT",         "adrSaveI","instrSub5"}, {"load162","adrlI","instrSub6"}, {"jmpAbsUT"              }, desc="Load a code pointer from memory at a given 16-bit address, then jump to that code."                                                    , ccode={"loadimm161","loadimm162","pushretaddr1","pushretaddr2","cpu.i=(wordut+cpu.a)%65536;cpu.u=readmemory(cpu.i);","cpu.t=readmemory((cpu.i+1)%65536);","jmpabsut"            } }, -- 0x2D
	{ mnem="JMP [ind,A]",opcode=0x4C,{"loadImm161","instrSub1"}, {"loadImm162","instrSub2"},                                                             {"load161","adrrUT","adrr2A","adrSaveI","instrSub3"}, {"load162","adrlI","instrSub4"}, {"jmpAbsUT"              }, desc="Load a subroutine pointer from memory at a given 16-bit address, then jump to that subroutine, saving the return address on the stack.", ccode={"loadimm161","loadimm162",                              "cpu.i=(wordut+cpu.a)%65536;cpu.u=readmemory(cpu.i);","cpu.t=readmemory((cpu.i+1)%65536);","jmpabsut"            } }, -- 0x6D
	{ mnem="JSR [ind,A]",opcode=0x0C,{"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushRetAddr1","instrSub3"}, {"pushRetAddr2","instrSub4"}, {"load161","adrrUT","adrr2A","adrSaveI","instrSub5"}, {"load162","adrlI","instrSub6"}, {"jmpAbsUT"              }, desc="Load a code pointer from memory at a given 16-bit address, then jump to that code."                                                    , ccode={"loadimm161","loadimm162","pushretaddr1","pushretaddr2","cpu.i=(wordut+cpu.a)%65536;cpu.u=readmemory(cpu.i);","cpu.t=readmemory((cpu.i+1)%65536);","jmpabsut"            } }, -- 0x2D
	{ mnem="JMP X"    , opcode=0x64,                                                                                                                                                                                                            {"jmpAbsP"               }, desc="Set the Program Counter to the 16-bit value in the X register, executing the code at that address"                                     , ccode={                                                                                                                                                   "jmpabsp"             } },
	{ mnem="JMP Y"    , opcode=0x44,                                                                                                                                                                                                            {"jmpAbsQ"               }, desc="Set the Program Counter to the 16-bit value in the Y register, executing the code at that address"                                     , ccode={                                                                                                                                                   "jmpabsq"             } },
--	{ mnem="jsy X"    , opcode=0x  ,                                                                                                                                                                                                            {"jmpAbsP" ,"saveRetAddr"}, desc="I=P, Q=I"                                                                                                                              , ccode={                                                                                                                                                   "jmpabsp  saveretaddr"} },
--	{ mnem="jsy Y"    , opcode=0x  ,                                                                                                                                                                                                            {"jmpAbsQ" ,"saveRetAddr"}, desc="I=Q, Q=I"                                                                                                                              , ccode={                                                                                                                                                   "jmpabsq  saveretaddr"} },
	{ mnem="JSR X"    , opcode=0x24,                                                         {"pushRetAddr1","instrSub1"}, {"pushRetAddr2","instrSub2"},                                                                                        {"jmpAbsP"               }, desc="Save the Program Counter on the Stack, then set it to %X, executing the code at that address"                                          , ccode={                          "pushretaddr1","pushretaddr2",                                                                                           "jmpabsp"             } },
	{ mnem="JSR Y"    , opcode=0x04,                                                         {"pushRetAddr1","instrSub1"}, {"pushRetAddr2","instrSub2"},                                                                                        {"jmpAbsQ"               }, desc="Save the Program Counter on the Stack, then set it to %Y, executing the code at that address"                                          , ccode={                          "pushretaddr1","pushretaddr2",                                                                                           "jmpabsq"             } },
	{ mnem="RTS"      , opcode=0x60, {"pop161"    ,"instrSub1"}, {"pop162"    ,"instrSub2"},                                                                                                                                                    {"jmpAbsUT","adrInc"     }, desc="Retrieve the Program Counter from the stack, returning to where the last JSR instruction was executed"                                 , ccode={"pop161"    ,"pop162"    ,                                                                                                                         "jmpabsutplus1"       } },
	
	{ category = "Stack", catlet="S" },
	{ mnem="PHA"      , opcode=0x48,                                   {"pushReg","alurA"  ,"instrSub1"}, {                    "instrNext"}, desc="Push %A onto the Stack"                                                               , ccode={"pushbyte(cpu.a);","lni;"} },
	{ mnem="PHB"      , opcode=0x5C,                                   {"pushReg","alurB"  ,"instrSub1"}, {                    "instrNext"}, desc="Push %B onto the Stack"                                                               , ccode={"pushbyte(cpu.b);","lni;"} },
	{ mnem="PHC"      , opcode=0x1C,                                   {"pushReg","alurC"  ,"instrSub1"}, {                    "instrNext"}, desc="Push %C onto the Stack"                                                               , ccode={"pushbyte(cpu.c);","lni;"} },
	{ mnem="PHP"      , opcode=0x08,                                   {"pushReg","alurF"  ,"instrSub1"}, {                    "instrNext"}, desc="Push a byte containing the Carry Flag and Zero Flag onto the Stack"                   , ccode={"int f = cpu.nz | (cpu.cf<<1); pushbyte(f);","lni;"} },
	{ mnem="PHX"      , opcode=0x54, {"pushReg","alurPH","instrSub1"}, {"pushReg","alurPL" ,"instrSub2"}, {                    "instrNext"}, desc="Push %X onto the Stack"                                                               , ccode={"push161(cpu.p);","push162(cpu.p);","lni;"} },
	{ mnem="PHY"      , opcode=0x14, {"pushReg","alurQH","instrSub1"}, {"pushReg","alurQL" ,"instrSub2"}, {                    "instrNext"}, desc="Push %Y onto the Stack"                                                               , ccode={"push161(cpu.q);","push162(cpu.q);","lni;"} },
	{ mnem="PLA"      , opcode=0x68,                                   {"popReg","memSaveA","instrSub1"}, {                    "instrNext"}, desc="Pull a byte from the Stack, and store it in the A register"                           , ccode={"cpu.a=popbyte;","lni;"} },
	{ mnem="PLB"      , opcode=0x7C,                                   {"popReg","memSaveB","instrSub1"}, {                    "instrNext"}, desc="Pull a byte from the Stack, and store it in the B register"                           , ccode={"cpu.b=popbyte;","lni;"} },
	{ mnem="PLC"      , opcode=0x3C,                                   {"popReg","memSaveC","instrSub1"}, {                    "instrNext"}, desc="Pull a byte from the Stack, and store it in the C register"                           , ccode={"cpu.c=popbyte;","lni;"} },
	{ mnem="PLP"      , opcode=0x28,                                   {"popReg","memSaveF","instrSub1"}, {                    "instrNext"}, desc="Pull a byte from the Stack, and use it to set the Carry Flag and Zero flag"           , ccode={"int f=popbyte; cpu.nz = f&1; cpu.cf = (f>>1)&1;","lni;"} },
	{ mnem="PLX"      , opcode=0x74, {"pop161",          "instrSub1"}, {"pop162",           "instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="Pull two bytes from the stack, and store the resulting 16-bit value in the X register", ccode={"pop161","pop162","cpu.p=wordut; lni;"} },
	{ mnem="PLY"      , opcode=0x34, {"pop161",          "instrSub1"}, {"pop162",           "instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Pull two bytes from the stack, and store the resulting 16-bit value in the Y register", ccode={"pop161","pop162","cpu.q=wordut; lni;"} },
--	{ mnem="psh imm8" , opcode=0x  , {"loadImmedT","instrSub1"}, {"pushReg","alurT","instrSub2"}, {"instrNext"}, desc="*(S++)=imm8", ccode={"loadimmedt;","pushbyte(cpu.t);","lni;"} },
--	{ mnem="phw imm16", opcode=0x  , {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"pushReg","alurU","instrSub3"}, {"pushReg","alurT","instrSub4"}, {"instrNext"}, desc="*(S++++)=imm16", ccode={"loadimm161","loadimm162","pushbyte(cpu.u);","pushbyte(cpu.t);","lni;"} }, -- 0x3D
	
	{ category = "8-bit Load/Store", catlet="B" },
	{ mnem="LDA #"    , opcode=0xA9,                                                         {"loadImmed"    ,            "memSaveA",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the A register to %imm8"                , ccode={"cpu.a=loadimmed; setzf(cpu.a);","lni;"} },
	{ mnem="LDB #"    , opcode=0xAB,                                                         {"loadImmed"    ,            "memSaveB",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the B register to %imm8"                , ccode={"cpu.b=loadimmed; setzf(cpu.b);","lni;"} },
	{ mnem="LDC #"    , opcode=0x2B,                                                         {"loadImmed"    ,            "memSaveC",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the C register to %imm8"                , ccode={"cpu.c=loadimmed; setzf(cpu.c);","lni;"} },
	{ mnem="LDA zpg"  , opcode=0xA5,                             {"loadImmedT","instrSub1"}, {"loadStackRel" ,            "memSaveA",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the A register to %zpgIn, %zFlgMem"     , ccode={"loadimmedt;","cpu.a=loadstackrel; setzf(cpu.a);","lni;"} },
	{ mnem="LDB zpg"  , opcode=0xA7,                             {"loadImmedT","instrSub1"}, {"loadStackRel" ,            "memSaveB",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the B register to %zpgIn, %zFlgMem"     , ccode={"loadimmedt;","cpu.b=loadstackrel; setzf(cpu.b);","lni;"} },
	{ mnem="LDC zpg"  , opcode=0x27,                             {"loadImmedT","instrSub1"}, {"loadStackRel" ,            "memSaveC",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the C register to %zpgIn, %zFlgMem"     , ccode={"loadimmedt;","cpu.c=loadstackrel; setzf(cpu.c);","lni;"} },
	{ mnem="STA zpg"  , opcode=0x85,                             {"loadImmedT","instrSub1"}, {"storeStackRel",            "alurA",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %zpg"                 , ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="STB zpg"  , opcode=0x87,                             {"loadImmedT","instrSub1"}, {"storeStackRel",            "alurB",                         "instrSub2"}, {"instrNext"}, desc="Store %B in memory at %zpg"                 , ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="STC zpg"  , opcode=0x07,                             {"loadImmedT","instrSub1"}, {"storeStackRel",            "alurC",                         "instrSub2"}, {"instrNext"}, desc="Store %C in memory at %zpg"                 , ccode={"loadimmedt;","storestackrel(cpu.a);","lni;"} },
	{ mnem="LDA abs"  , opcode=0xED, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "loadReg" ,"memSaveA",       "memSaveFlags","instrSub3"}, {"instrNext"}, desc="Set the A register to %absIn, %zFlgMem"     , ccode={"loadimm161","loadimm162","cpu.a=loadut; setzf(cpu.a);", "lni;"} },
	{ mnem="LDB abs"  , opcode=0xEF, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "loadReg" ,"memSaveB",       "memSaveFlags","instrSub3"}, {"instrNext"}, desc="Set the B register to %absIn, %zFlgMem"     , ccode={"loadimm161","loadimm162","cpu.b=loadut; setzf(cpu.b);", "lni;"} },
	{ mnem="LDC abs"  , opcode=0x6F, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "loadReg" ,"memSaveC",       "memSaveFlags","instrSub3"}, {"instrNext"}, desc="Set the C register to %absIn, %zFlgMem"     , ccode={"loadimm161","loadimm162","cpu.c=loadut; setzf(cpu.c);", "lni;"} },
	{ mnem="STA abs"  , opcode=0xCD, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "storeReg","alurA",                         "instrSub3"}, {"instrNext"}, desc="Store %A in memory at %abs"                 , ccode={"loadimm161","loadimm162","storeut(cpu.a);",             "lni;"} },
	{ mnem="STB abs"  , opcode=0xCF, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "storeReg","alurB",                         "instrSub3"}, {"instrNext"}, desc="Store %B in memory at %abs"                 , ccode={"loadimm161","loadimm162","storeut(cpu.b);",             "lni;"} },
	{ mnem="STC abs"  , opcode=0x4F, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"adrrUT",        "storeReg","alurC",                         "instrSub3"}, {"instrNext"}, desc="Store %C in memory at %abs"                 , ccode={"loadimm161","loadimm162","storeut(cpu.c);",             "lni;"} },
	{ mnem="LDA X"    , opcode=0xA1,                                                         {"adrlP",         "loadReg" ,"memSaveA",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the A register to %xIn, %zFlgMem"       , ccode={"cpu.a=loadp; setzf(cpu.a);","lni;"} },
	{ mnem="LDB X"    , opcode=0xA3,                                                         {"adrlP",         "loadReg" ,"memSaveB",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the B register to %xIn, %zFlgMem"       , ccode={"cpu.b=loadp; setzf(cpu.b);","lni;"} },
	{ mnem="LDC X"    , opcode=0x23,                                                         {"adrlP",         "loadReg" ,"memSaveC",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the C register to %xIn, %zFlgMem"       , ccode={"cpu.c=loadp; setzf(cpu.c);","lni;"} },
	{ mnem="LDA Y"    , opcode=0xB1,                                                         {"adrlQ",         "loadReg" ,"memSaveA",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the A register to %yIn, %zFlgMem"       , ccode={"cpu.a=loadq; setzf(cpu.a);","lni;"} },
	{ mnem="LDB Y"    , opcode=0xB3,                                                         {"adrlQ",         "loadReg" ,"memSaveB",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the B register to %yIn, %zFlgMem"       , ccode={"cpu.b=loadq; setzf(cpu.b);","lni;"} },
	{ mnem="LDC Y"    , opcode=0x33,                                                         {"adrlQ",         "loadReg" ,"memSaveC",       "memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the C register to %yIn, %zFlgMem"       , ccode={"cpu.c=loadq; setzf(cpu.c);","lni;"} },
	{ mnem="STA X"    , opcode=0x81,                                                         {"adrlP",         "storeReg","alurA",                         "instrSub1"}, {"instrNext"}, desc="Store %A in memory at %adrX"                , ccode={"storep(cpu.a);","lni;"} },
	{ mnem="STB X"    , opcode=0x83,                                                         {"adrlP",         "storeReg","alurB",                         "instrSub1"}, {"instrNext"}, desc="Store %B in memory at %adrX"                , ccode={"storep(cpu.b);","lni;"} },
	{ mnem="STC X"    , opcode=0x03,                                                         {"adrlP",         "storeReg","alurC",                         "instrSub1"}, {"instrNext"}, desc="Store %C in memory at %adrX"                , ccode={"storep(cpu.c);","lni;"} },
	{ mnem="STA Y"    , opcode=0x91,                                                         {"adrlQ",         "storeReg","alurA",                         "instrSub1"}, {"instrNext"}, desc="Store %A in memory at %adrY"                , ccode={"storeq(cpu.a);","lni;"} },
	{ mnem="STB Y"    , opcode=0x93,                                                         {"adrlQ",         "storeReg","alurB",                         "instrSub1"}, {"instrNext"}, desc="Store %B in memory at %adrY"                , ccode={"storeq(cpu.b);","lni;"} },
	{ mnem="STC Y"    , opcode=0x13,                                                         {"adrlQ",         "storeReg","alurC",                         "instrSub1"}, {"instrNext"}, desc="Store %C in memory at %adrY"                , ccode={"storeq(cpu.c);","lni;"} },
	{ mnem="LDA X+"   , opcode=0xE1,                                                         {"adrlP",         "loadReg" ,"memSaveA","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the A register to %xIn, %xInc, %zFlgMem", ccode={"cpu.a=loadpinc; setzf(cpu.a);","lni;"} },
	{ mnem="LDB X+"   , opcode=0xE3,                                                         {"adrlP",         "loadReg" ,"memSaveB","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the B register to %xIn, %xInc, %zFlgMem", ccode={"cpu.b=loadpinc; setzf(cpu.b);","lni;"} },
	{ mnem="LDC X+"   , opcode=0x63,                                                         {"adrlP",         "loadReg" ,"memSaveC","incP","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the C register to %xIn, %xInc, %zFlgMem", ccode={"cpu.c=loadpinc; setzf(cpu.c);","lni;"} },
	{ mnem="LDA Y+"   , opcode=0xF1,                                                         {"adrlQ",         "loadReg" ,"memSaveA","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the A register to %yIn, %yInc, %zFlgMem", ccode={"cpu.a=loadqinc; setzf(cpu.a);","lni;"} },
	{ mnem="LDB Y+"   , opcode=0xF3,                                                         {"adrlQ",         "loadReg" ,"memSaveB","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the B register to %yIn, %yInc, %zFlgMem", ccode={"cpu.b=loadqinc; setzf(cpu.b);","lni;"} },
	{ mnem="LDC Y+"   , opcode=0x73,                                                         {"adrlQ",         "loadReg" ,"memSaveC","incQ","memSaveFlags","instrSub1"}, {"instrNext"}, desc="Set the C register to %yIn, %yInc, %zFlgMem", ccode={"cpu.c=loadqinc; setzf(cpu.c);","lni;"} },
	{ mnem="STA X+"   , opcode=0xC1,                                                         {"adrlP",         "storeReg","alurA",   "incP",               "instrSub1"}, {"instrNext"}, desc="Store %A in memory at %adrX, and %xInc"     , ccode={"storepinc(cpu.a);","lni;"} },
	{ mnem="STB X+"   , opcode=0xC3,                                                         {"adrlP",         "storeReg","alurB",   "incP",               "instrSub1"}, {"instrNext"}, desc="Store %B in memory at %adrX, and %xInc"     , ccode={"storepinc(cpu.b);","lni;"} },
	{ mnem="STC X+"   , opcode=0x43,                                                         {"adrlP",         "storeReg","alurC",   "incP",               "instrSub1"}, {"instrNext"}, desc="Store %C in memory at %adrX, and %xInc"     , ccode={"storepinc(cpu.c);","lni;"} },
	{ mnem="STA Y+"   , opcode=0xD1,                                                         {"adrlQ",         "storeReg","alurA",   "incQ",               "instrSub1"}, {"instrNext"}, desc="Store %A in memory at %adrY, and %yInc"     , ccode={"storeqinc(cpu.a);","lni;"} },
	{ mnem="STB Y+"   , opcode=0xD3,                                                         {"adrlQ",         "storeReg","alurB",   "incQ",               "instrSub1"}, {"instrNext"}, desc="Store %B in memory at %adrY, and %yInc"     , ccode={"storeqinc(cpu.b);","lni;"} },
	{ mnem="STC Y+"   , opcode=0x53,                                                         {"adrlQ",         "storeReg","alurC",   "incQ",               "instrSub1"}, {"instrNext"}, desc="Store %C in memory at %adrY, and %yInc"     , ccode={"storeqinc(cpu.c);","lni;"} },
	{ mnem="LDA X,ofs", opcode=0xBD,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","loadReg" ,"memSaveA",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the A register to %XofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.a=loadput; setzf(cpu.a);","lni;"} },
	{ mnem="LDB X,ofs", opcode=0xBF,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","loadReg" ,"memSaveB",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the B register to %XofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.b=loadput; setzf(cpu.b);","lni;"} },
	{ mnem="LDC X,ofs", opcode=0x3F,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","loadReg" ,"memSaveC",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the C register to %XofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.c=loadput; setzf(cpu.c);","lni;"} },
	{ mnem="LDA Y,ofs", opcode=0xB9,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","loadReg" ,"memSaveA",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the A register to %YofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.a=loadqut; setzf(cpu.a);","lni;"} },
	{ mnem="LDB Y,ofs", opcode=0xBB,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","loadReg" ,"memSaveB",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the B register to %YofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.b=loadqut; setzf(cpu.b);","lni;"} },
	{ mnem="LDC Y,ofs", opcode=0x3B,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","loadReg" ,"memSaveC",       "memSaveFlags","instrSub2"}, {"instrNext"}, desc="Set the C register to %YofsIn, %zFlgMem"    , ccode={"loadimm161","loadimm162","cpu.c=loadqut; setzf(cpu.c);","lni;"} },
	{ mnem="STA X,ofs", opcode=0x9D,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","storeReg","alurA",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Xofs"                , ccode={"loadimm161","loadimm162","storeput(cpu.a);",            "lni;"} },
	{ mnem="STB X,ofs", opcode=0x9F,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","storeReg","alurB",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Xofs"                , ccode={"loadimm161","loadimm162","storeput(cpu.b);",            "lni;"} },
	{ mnem="STC X,ofs", opcode=0x1F,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","storeReg","alurC",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Xofs"                , ccode={"loadimm161","loadimm162","storeput(cpu.c);",            "lni;"} },
	{ mnem="STA Y,ofs", opcode=0x99,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","storeReg","alurA",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Yofs"                , ccode={"loadimm161","loadimm162","storequt(cpu.a);",            "lni;"} },
	{ mnem="STB Y,ofs", opcode=0x9B,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","storeReg","alurB",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Yofs"                , ccode={"loadimm161","loadimm162","storequt(cpu.b);",            "lni;"} },
	{ mnem="STC Y,ofs", opcode=0x1B,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","storeReg","alurC",                         "instrSub2"}, {"instrNext"}, desc="Store %A in memory at %Yofs"                , ccode={"loadimm161","loadimm162","storequt(cpu.c);",            "lni;"} },

	{ category = "16-bit Load/Store", catlet="W" },
	{ mnem="LDX ##"   , opcode=0xAA,                                                         {"loadImm161"                          ,"instrSub1"}, {"loadImm162"                                   ,"instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %imm16"         , ccode={"loadimm161","loadimm162","cpu.p=wordut; lni;"} },
	{ mnem="LDY ##"   , opcode=0xA8,                                                         {"loadImm161"                          ,"instrSub1"}, {"loadImm162"                                   ,"instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the X register to %imm16"         , ccode={"loadimm161","loadimm162","cpu.q=wordut; lni;"} },
--	{ mnem="lds imm16", opcode=0x  ,                                                         {"loadImm161"                          ,"instrSub1"}, {"loadImm162"                                   ,"instrSub2"}, {"adwrUT","adwSaveS","instrNext"}, desc="S=imm16"                              , ccode={"loadimm161","loadimm162","cpu.s=wordut; lni;"} },
--	{ mnem="ldv imm16", opcode=0x  ,                                                         {"loadImm161"                          ,"instrSub1"}, {"loadImm162"                                   ,"instrSub2"}, {"adwrUT","adwSaveV","instrNext"}, desc="V=imm16"                              , ccode={"loadimm161","loadimm162","cpu.v=wordut; lni;"} },
	{ mnem="LDX zpg"  , opcode=0xA6,                             {"loadImmedT","instrSub1"}, {"loadStackRel161"                     ,"instrSub2"}, {"loadStackRel162"                              ,"instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %zpgIn16"       , ccode={"loadimmedt","loadstackrel161","loadstackrel162","cpu.p=wordut; lni;"} },
	{ mnem="LDY zpg"  , opcode=0xA4,                             {"loadImmedT","instrSub1"}, {"loadStackRel161"                     ,"instrSub2"}, {"loadStackRel162"                              ,"instrSub3"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the Y register to %zpgIn16"       , ccode={"loadimmedt","loadstackrel161","loadstackrel162","cpu.p=wordut; lni;"} },
	{ mnem="STX zpg"  , opcode=0x86,                             {"loadImmedT","instrSub1"}, {"storeStackRel161"         ,"alurPH"  ,"instrSub2"}, {"storeStackRel162"                  ,"alurPL"  ,"instrSub3"}, {                    "instrNext"}, desc="Store %X in memory at %zpg"           , ccode={"loadimmedt","storestackrel161(cpu.p);","storestackrel162(cpu.p);","lni;"} },
	{ mnem="STY zpg"  , opcode=0x84,                             {"loadImmedT","instrSub1"}, {"storeStackRel161"         ,"alurQH"  ,"instrSub2"}, {"storeStackRel162"                  ,"alurQL"  ,"instrSub3"}, {                    "instrNext"}, desc="Store %Y in memory at %zpg"           , ccode={"loadimmedt","storestackrel161(cpu.q);","storestackrel162(cpu.q);","lni;"} },
	{ mnem="LDX abs"  , opcode=0xAE, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"loadUTU","adwIncUT"       ,"adwSaveP","instrSub3"}, {"adrlP","loadRegT"                             ,"instrSub4"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %absIn16"       , ccode={"loadimm161","loadimm162","cpu.p=wordut; cpu.u=loadut;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} }, -- 0x69
	{ mnem="LDY abs"  , opcode=0xAC, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"loadUTU","adwIncUT"       ,"adwSaveQ","instrSub3"}, {"adrlQ","loadRegT"                             ,"instrSub4"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the Y register to %absIn16"       , ccode={"loadimm161","loadimm162","cpu.q=wordut; cpu.u=loadut;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} }, -- 0x6B
	{ mnem="STX abs"  , opcode=0x8E, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"storeUT"                  ,"alurPH"  ,"instrSub3"}, {"storeUT","adrInc"                  ,"alurPL"  ,"instrSub4"}, {                    "instrNext"}, desc="Store %X in memory at %abs"           , ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.p));","storeutp1(lobyte(cpu.p));","lni;"       } }, -- 0x6D
	{ mnem="STY abs"  , opcode=0x8C, {"loadImm161","instrSub1"}, {"loadImm162","instrSub2"}, {"storeUT"                  ,"alurQH"  ,"instrSub3"}, {"storeUT","adrInc"                  ,"alurQL"  ,"instrSub4"}, {                    "instrNext"}, desc="Store %X in memory at %abs"           , ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.q));","storeutp1(lobyte(cpu.q));","lni;"       } }, -- 0x6F
	{ mnem="LDX X,ofs", opcode=0xBE,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","loadReg" ,"memSaveU","instrSub2"}, {"adrlP","adrrlT","adrInc","loadReg" ,"memSaveT","instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %XofsIn16"      , ccode={"loadimm161","loadimm162","cpu.p=wordut; cpu.u=loadut;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} },
	{ mnem="LDX Y,ofs", opcode=0xBA,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","loadReg" ,"memSaveU","instrSub2"}, {"adrlP","adrrlT","adrInc","loadReg" ,"memSaveT","instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the Y register to %XofsIn16"      , ccode={"loadimm161","loadimm162","cpu.q=wordut; cpu.u=loadut;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} },
	{ mnem="LDY X,ofs", opcode=0xBC,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","loadReg" ,"memSaveU","instrSub2"}, {"adrlP","adrrlT","adrInc","loadReg" ,"memSaveT","instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %YofsIn16"      , ccode={"loadimm161","loadimm162","cpu.p=wordut; cpu.u=loadut;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} },
	{ mnem="LDY Y,ofs", opcode=0xB8,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","loadReg" ,"memSaveU","instrSub2"}, {"adrlP","adrrlT","adrInc","loadReg" ,"memSaveT","instrSub3"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the Y register to %YofsIn16"      , ccode={"loadimm161","loadimm162","cpu.q=wordut; cpu.u=loadut;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} },
	{ mnem="STX Y,ofs", opcode=0x9A,                             {"loadImmedT","instrSub1"}, {"adrlQ","adrrlT","storeReg","alurPH"  ,"instrSub2"}, {"adrlP","adrrlT","adrInc","storeReg","alurPL"  ,"instrSub3"}, {                    "instrNext"}, desc="Store %X in memory at %Yofs"          , ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.p));","storeutp1(lobyte(cpu.p));","lni;"       } },
	{ mnem="STY X,ofs", opcode=0x9C,                             {"loadImmedT","instrSub1"}, {"adrlP","adrrlT","storeReg","alurQH"  ,"instrSub2"}, {"adrlP","adrrlT","adrInc","storeReg","alurQL"  ,"instrSub3"}, {                    "instrNext"}, desc="Store %Y in memory at %Xofs"          , ccode={"loadimm161","loadimm162","storeut(hibyte(cpu.q));","storeutp1(lobyte(cpu.q));","lni;"       } },
	{ mnem="LDX X"    , opcode=0xA2,                                                         {"adrlP","load161"                     ,"instrSub1"}, {"adrlP","load162"                              ,"instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %Xin16"         , ccode={"cpu.u=loadp;","cpu.t=loadpp1;","cpu.p=wordut; lni;"} },
	{ mnem="LDY X"    , opcode=0xA0,                                                         {"adrlP","load161"                     ,"instrSub1"}, {"adrlP","load162"                              ,"instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the Y register to %Xin16"         , ccode={"cpu.u=loadp;","cpu.t=loadpp1;","cpu.q=wordut; lni;"} },
	{ mnem="LDX Y"    , opcode=0xB2,                                                         {"adrlQ","load161"                     ,"instrSub1"}, {"adrlQ","load162"                              ,"instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %Yin16"         , ccode={"cpu.u=loadq;","cpu.t=loadqp1;","cpu.p=wordut; lni;"} },
	{ mnem="LDY Y"    , opcode=0xE2,                                                         {"adrlQ","load161"                     ,"instrSub1"}, {"adrlQ","load162"                              ,"instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the Y register to %Yin16"         , ccode={"cpu.u=loadq;","cpu.t=loadqp1;","cpu.q=wordut; lni;"} },
	{ mnem="STX Y"    , opcode=0x92,                                                         {"adrlQ","store161"         ,"alurPH"  ,"instrSub1"}, {"adrlQ","store162"                  ,"alurPL"  ,"instrSub2"}, {                    "instrNext"}, desc="Store %X in memory at %adrY"          , ccode={"storeq(hibyte(cpu.p));","storeqp1(lobyte(cpu.p));","lni;"} },
	{ mnem="STY X"    , opcode=0x80,                                                         {"adrlP","store161"         ,"alurQH"  ,"instrSub1"}, {"adrlP","store162"                  ,"alurQL"  ,"instrSub2"}, {                    "instrNext"}, desc="Store %Y in memory at %adrX"          , ccode={"storep(hibyte(cpu.q));","storepp1(lobyte(cpu.q));","lni;"} },
	{ mnem="LDX Y+"   , opcode=0xF2,                                                         {"adrlQ","load161"                     ,"instrSub1"}, {"adrlQ","load162" ,"incQ2"                     ,"instrSub2"}, {"adwrUT","adwSaveP","instrNext"}, desc="Set the X register to %Yin16, %Yinc16", ccode={"cpu.u=loadqinc;","cpu.t=loadqinc;","cpu.p=wordut; lni;"} },
	{ mnem="LDY X+"   , opcode=0xE0,                                                         {"adrlP","load161"                     ,"instrSub1"}, {"adrlP","load162" ,"incP2"                     ,"instrSub2"}, {"adwrUT","adwSaveQ","instrNext"}, desc="Set the Y register to %Xin16, %Xinc16", ccode={"cpu.u=loadpinc;","cpu.t=loadpinc;","cpu.q=wordut; lni;"} },
	{ mnem="STX Y+"   , opcode=0xD2,                                                         {"adrlQ","store161"         ,"alurPH"  ,"instrSub1"}, {"adrlQ","store162","incQ2"          ,"alurPL"  ,"instrSub2"}, {                    "instrNext"}, desc="Store %X in memory at %adrY, %Yinc16" , ccode={"storeqinc(hibyte(cpu.p));","storeqinc(lobyte(cpu.p));","lni;"} },
	{ mnem="STY X+"   , opcode=0xC0,                                                         {"adrlP","store161"         ,"alurQH"  ,"instrSub1"}, {"adrlP","store162","incP2"          ,"alurQL"  ,"instrSub2"}, {                    "instrNext"}, desc="Store %Y in memory at %adrX, %Xinc16" , ccode={"storepinc(hibyte(cpu.q));","storepinc(lobyte(cpu.q));","lni;"} },
	
	{ category = "Moves", catlet="M" },
	{ mnem="TBA"      , opcode=0x97, {"alurB" ,"aluOpMov","aluSaveA","instrNext"}, desc="Copy %B into the A register", ccode={"cpu.a=cpu.b; lni;"} },
	{ mnem="TCA"      , opcode=0x17, {"alurC" ,"aluOpMov","aluSaveA","instrNext"}, desc="Copy %C into the A register", ccode={"cpu.a=cpu.c; lni;"} },
	{ mnem="TAB"      , opcode=0xB7, {"alurA" ,"aluOpMov","aluSaveB","instrNext"}, desc="Copy %A into the B register", ccode={"cpu.b=cpu.a; lni;"} },
	{ mnem="TCB"      , opcode=0xD7, {"alurC" ,"aluOpMov","aluSaveB","instrNext"}, desc="Copy %C into the B register", ccode={"cpu.b=cpu.c; lni;"} },
	{ mnem="TAC"      , opcode=0x37, {"alurA" ,"aluOpMov","aluSaveC","instrNext"}, desc="Copy %A into the C register", ccode={"cpu.c=cpu.a; lni;"} },
	{ mnem="TBC"      , opcode=0xF7, {"alurB" ,"aluOpMov","aluSaveC","instrNext"}, desc="Copy %B into the C register", ccode={"cpu.c=cpu.b; lni;"} },
--	{ mnem="lda pl"   , opcode=0x  , {"alurPL","aluOpMov","aluSaveA","instrNext"}, desc="A=P&FF"                     , ccode={"cpu.a=lobyte(cpu.p); lni;"} },
--	{ mnem="lda ph"   , opcode=0x  , {"alurPH","aluOpMov","aluSaveA","instrNext"}, desc="A=P>>8"                     , ccode={"cpu.a=hibyte(cpu.p); lni;"} },
--	{ mnem="lda ql"   , opcode=0x  , {"alurQL","aluOpMov","aluSaveA","instrNext"}, desc="A=Q&FF"                     , ccode={"cpu.a=lobyte(cpu.q); lni;"} },
--	{ mnem="lda qh"   , opcode=0x  , {"alurQH","aluOpMov","aluSaveA","instrNext"}, desc="A=Q>>8"                     , ccode={"cpu.a=hibyte(cpu.q); lni;"} },
--	{ mnem="ldb pl"   , opcode=0x  , {"alurPL","aluOpMov","aluSaveB","instrNext"}, desc="B=P&FF"                     , ccode={"cpu.b=lobyte(cpu.p); lni;"} },
--	{ mnem="ldc ph"   , opcode=0x  , {"alurPH","aluOpMov","aluSaveC","instrNext"}, desc="C=P>>8"                     , ccode={"cpu.c=hibyte(cpu.p); lni;"} },
--	{ mnem="ldb ql"   , opcode=0x  , {"alurQL","aluOpMov","aluSaveB","instrNext"}, desc="B=Q&FF"                     , ccode={"cpu.b=lobyte(cpu.q); lni;"} },
--	{ mnem="ldc qh"   , opcode=0x  , {"alurQH","aluOpMov","aluSaveC","instrNext"}, desc="C=Q>>8"                     , ccode={"cpu.c=hibyte(cpu.q); lni;"} },
	{ mnem="TYX"      , opcode=0xB4, {"adwlQ" ,           "adwSaveP","instrNext"}, desc="Copy %Y into the 16-bit X register", ccode={"cpu.p=cpu.q; lni;"} },
	{ mnem="TXY"      , opcode=0x94, {"adwlP" ,           "adwSaveQ","instrNext"}, desc="Copy %X into the 16-bit Y register", ccode={"cpu.q=cpu.p; lni;"} },
	{ mnem="TVX"      , opcode=0xB6, {"adwlV" ,           "adwSaveP","instrNext"}, desc="Copy the 16-bit Interrupt Return Address into the X register", ccode={"cpu.v=cpu.p; lni;"} },
	{ mnem="TXV"      , opcode=0x96, {"adwlP" ,           "adwSaveV","instrNext"}, desc="Copy %X into the 16-bit Interrupt Return Address register", ccode={"cpu.p=cpu.v; lni;"} },
--	{ mnem="ldp i"    , opcode=0x  , {"adwlI" ,           "adwSaveP","instrNext"}, desc="P=I", ccode={"cpu.p=cpu.i; lni;"} },
--	{ mnem="ldp cb"   , opcode=0x  , {"adwrCB",           "adwSaveP","instrNext"}, desc="P=(C<<8)+B", ccode={"cpu.p=wordcb; lni;"} },
--	{ mnem="ldq cb"   , opcode=0x  , {"adwrCB",           "adwSaveQ","instrNext"}, desc="Q=(C<<8)+B", ccode={"cpu.q=wordcb; lni;"} },
	{ mnem="TAS"      , opcode=0x95, {"adwrlA",           "adwSaveS","instrNext"}, desc="Copy %A into the 8-bit Stack Pointer register", ccode={"cpu.p=cpu.s; lni;"} },
	{ mnem="TSA"      , opcode=0xB5, {"alurSL","aluOpMov","aluSaveB","instrNext"}, desc="Copy the 8-bit Stack Pointer into the A register", ccode={"cpu.s=cpu.p; lni;"} },
}

if not __ARCH_INCLUDED then
	local arch8608 = require("8608-definition")
	arch8608.instructions = instructions
	local gen = require("generate-architecture")
	gen(arch8608, true, true)
end

return instructions
