make states numbers instead of booleans
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@@ -18,9 +18,9 @@ datablock fxDTSBrickData(LogicGate_FullAdder_Data)
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logicUpdate =
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"return function(gate) " @
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" local a, b, c = bool_to_int[Gate.getportstate(gate, 1)], bool_to_int[Gate.getportstate(gate, 2)], bool_to_int[Gate.getportstate(gate, 3)] " @
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" Gate.setportstate(gate, 4, bit.bxor(bit.bxor(a, b), c) == 1) " @
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" Gate.setportstate(gate, 5, bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b)) == 1) " @
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" local a, b, c = Gate.getportstate(gate, 1), Gate.getportstate(gate, 2), Gate.getportstate(gate, 3) " @
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" Gate.setportstate(gate, 4, bit.bxor(bit.bxor(a, b), c)) " @
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" Gate.setportstate(gate, 5, bit.bor(bit.bor(bit.band(b, c), bit.band(a, c)), bit.band(a, b))) " @
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"end"
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;
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