add enabler, wider buses, and pixel brick
This commit is contained in:
Redo
617
bricks/gen/newcode/Buffer 48 Bit.cs
Normal file
617
bricks/gen/newcode/Buffer 48 Bit.cs
Normal file
@@ -0,0 +1,617 @@
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datablock fxDtsBrickData(LogicGate_Buffer48_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 48 Bit.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 48 Bit";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 48 Bit";
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logicUIName = "Buffer 48 Bit";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "48 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if gate.ports[97].state then " @
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" gate.ports[49]:setstate(gate.ports[1].state) " @
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" gate.ports[50]:setstate(gate.ports[2].state) " @
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" gate.ports[51]:setstate(gate.ports[3].state) " @
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" gate.ports[52]:setstate(gate.ports[4].state) " @
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" gate.ports[53]:setstate(gate.ports[5].state) " @
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" gate.ports[54]:setstate(gate.ports[6].state) " @
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" gate.ports[55]:setstate(gate.ports[7].state) " @
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" gate.ports[56]:setstate(gate.ports[8].state) " @
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" gate.ports[57]:setstate(gate.ports[9].state) " @
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" gate.ports[58]:setstate(gate.ports[10].state) " @
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" gate.ports[59]:setstate(gate.ports[11].state) " @
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" gate.ports[60]:setstate(gate.ports[12].state) " @
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" gate.ports[61]:setstate(gate.ports[13].state) " @
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" gate.ports[62]:setstate(gate.ports[14].state) " @
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" gate.ports[63]:setstate(gate.ports[15].state) " @
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" gate.ports[64]:setstate(gate.ports[16].state) " @
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" gate.ports[65]:setstate(gate.ports[17].state) " @
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" gate.ports[66]:setstate(gate.ports[18].state) " @
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" gate.ports[67]:setstate(gate.ports[19].state) " @
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" gate.ports[68]:setstate(gate.ports[20].state) " @
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" gate.ports[69]:setstate(gate.ports[21].state) " @
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" gate.ports[70]:setstate(gate.ports[22].state) " @
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" gate.ports[71]:setstate(gate.ports[23].state) " @
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" gate.ports[72]:setstate(gate.ports[24].state) " @
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" gate.ports[73]:setstate(gate.ports[25].state) " @
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" gate.ports[74]:setstate(gate.ports[26].state) " @
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" gate.ports[75]:setstate(gate.ports[27].state) " @
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" gate.ports[76]:setstate(gate.ports[28].state) " @
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" gate.ports[77]:setstate(gate.ports[29].state) " @
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" gate.ports[78]:setstate(gate.ports[30].state) " @
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" gate.ports[79]:setstate(gate.ports[31].state) " @
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" gate.ports[80]:setstate(gate.ports[32].state) " @
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" gate.ports[81]:setstate(gate.ports[33].state) " @
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" gate.ports[82]:setstate(gate.ports[34].state) " @
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" gate.ports[83]:setstate(gate.ports[35].state) " @
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" gate.ports[84]:setstate(gate.ports[36].state) " @
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" gate.ports[85]:setstate(gate.ports[37].state) " @
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" gate.ports[86]:setstate(gate.ports[38].state) " @
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" gate.ports[87]:setstate(gate.ports[39].state) " @
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" gate.ports[88]:setstate(gate.ports[40].state) " @
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" gate.ports[89]:setstate(gate.ports[41].state) " @
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" gate.ports[90]:setstate(gate.ports[42].state) " @
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" gate.ports[91]:setstate(gate.ports[43].state) " @
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" gate.ports[92]:setstate(gate.ports[44].state) " @
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" gate.ports[93]:setstate(gate.ports[45].state) " @
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" gate.ports[94]:setstate(gate.ports[46].state) " @
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" gate.ports[95]:setstate(gate.ports[47].state) " @
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" gate.ports[96]:setstate(gate.ports[48].state) " @
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" else " @
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" gate.ports[49]:setstate(false) " @
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" gate.ports[50]:setstate(false) " @
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" gate.ports[51]:setstate(false) " @
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" gate.ports[52]:setstate(false) " @
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" gate.ports[53]:setstate(false) " @
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" gate.ports[54]:setstate(false) " @
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" gate.ports[55]:setstate(false) " @
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" gate.ports[56]:setstate(false) " @
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" gate.ports[57]:setstate(false) " @
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" gate.ports[58]:setstate(false) " @
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" gate.ports[59]:setstate(false) " @
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" gate.ports[60]:setstate(false) " @
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" gate.ports[61]:setstate(false) " @
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" gate.ports[62]:setstate(false) " @
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" gate.ports[63]:setstate(false) " @
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" gate.ports[64]:setstate(false) " @
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" gate.ports[65]:setstate(false) " @
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" gate.ports[66]:setstate(false) " @
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" gate.ports[67]:setstate(false) " @
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" gate.ports[68]:setstate(false) " @
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" gate.ports[69]:setstate(false) " @
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" gate.ports[70]:setstate(false) " @
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" gate.ports[71]:setstate(false) " @
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" gate.ports[72]:setstate(false) " @
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" gate.ports[73]:setstate(false) " @
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" gate.ports[74]:setstate(false) " @
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" gate.ports[75]:setstate(false) " @
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" gate.ports[76]:setstate(false) " @
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" gate.ports[77]:setstate(false) " @
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" gate.ports[78]:setstate(false) " @
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" gate.ports[79]:setstate(false) " @
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" gate.ports[80]:setstate(false) " @
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" gate.ports[81]:setstate(false) " @
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" gate.ports[82]:setstate(false) " @
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" gate.ports[83]:setstate(false) " @
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" gate.ports[84]:setstate(false) " @
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" gate.ports[85]:setstate(false) " @
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" gate.ports[86]:setstate(false) " @
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" gate.ports[87]:setstate(false) " @
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" gate.ports[88]:setstate(false) " @
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" gate.ports[89]:setstate(false) " @
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" gate.ports[90]:setstate(false) " @
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" gate.ports[91]:setstate(false) " @
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" gate.ports[92]:setstate(false) " @
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" gate.ports[93]:setstate(false) " @
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" gate.ports[94]:setstate(false) " @
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" gate.ports[95]:setstate(false) " @
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" gate.ports[96]:setstate(false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 97;
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logicPortType[0] = 1;
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logicPortPos[0] = "47 0 0";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 1;
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logicPortPos[1] = "45 0 0";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "In1";
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logicPortType[2] = 1;
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logicPortPos[2] = "43 0 0";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "In2";
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logicPortType[3] = 1;
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logicPortPos[3] = "41 0 0";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "In3";
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logicPortType[4] = 1;
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logicPortPos[4] = "39 0 0";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "In4";
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logicPortType[5] = 1;
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logicPortPos[5] = "37 0 0";
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logicPortDir[5] = 3;
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logicPortUIName[5] = "In5";
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logicPortType[6] = 1;
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logicPortPos[6] = "35 0 0";
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logicPortDir[6] = 3;
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logicPortUIName[6] = "In6";
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logicPortType[7] = 1;
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logicPortPos[7] = "33 0 0";
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logicPortDir[7] = 3;
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logicPortUIName[7] = "In7";
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logicPortType[8] = 1;
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logicPortPos[8] = "31 0 0";
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logicPortDir[8] = 3;
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logicPortUIName[8] = "In8";
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logicPortType[9] = 1;
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logicPortPos[9] = "29 0 0";
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logicPortDir[9] = 3;
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logicPortUIName[9] = "In9";
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logicPortType[10] = 1;
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logicPortPos[10] = "27 0 0";
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logicPortDir[10] = 3;
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logicPortUIName[10] = "In10";
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logicPortType[11] = 1;
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logicPortPos[11] = "25 0 0";
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logicPortDir[11] = 3;
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logicPortUIName[11] = "In11";
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logicPortType[12] = 1;
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logicPortPos[12] = "23 0 0";
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logicPortDir[12] = 3;
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logicPortUIName[12] = "In12";
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logicPortType[13] = 1;
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logicPortPos[13] = "21 0 0";
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logicPortDir[13] = 3;
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logicPortUIName[13] = "In13";
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logicPortType[14] = 1;
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logicPortPos[14] = "19 0 0";
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logicPortDir[14] = 3;
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logicPortUIName[14] = "In14";
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logicPortType[15] = 1;
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logicPortPos[15] = "17 0 0";
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logicPortDir[15] = 3;
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logicPortUIName[15] = "In15";
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logicPortType[16] = 1;
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logicPortPos[16] = "15 0 0";
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logicPortDir[16] = 3;
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logicPortUIName[16] = "In16";
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logicPortType[17] = 1;
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logicPortPos[17] = "13 0 0";
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logicPortDir[17] = 3;
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logicPortUIName[17] = "In17";
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logicPortType[18] = 1;
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logicPortPos[18] = "11 0 0";
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logicPortDir[18] = 3;
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logicPortUIName[18] = "In18";
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logicPortType[19] = 1;
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logicPortPos[19] = "9 0 0";
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logicPortDir[19] = 3;
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logicPortUIName[19] = "In19";
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logicPortType[20] = 1;
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logicPortPos[20] = "7 0 0";
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logicPortDir[20] = 3;
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logicPortUIName[20] = "In20";
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logicPortType[21] = 1;
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logicPortPos[21] = "5 0 0";
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logicPortDir[21] = 3;
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logicPortUIName[21] = "In21";
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logicPortType[22] = 1;
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logicPortPos[22] = "3 0 0";
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logicPortDir[22] = 3;
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logicPortUIName[22] = "In22";
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logicPortType[23] = 1;
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logicPortPos[23] = "1 0 0";
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logicPortDir[23] = 3;
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logicPortUIName[23] = "In23";
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logicPortType[24] = 1;
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logicPortPos[24] = "-1 0 0";
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logicPortDir[24] = 3;
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logicPortUIName[24] = "In24";
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logicPortType[25] = 1;
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logicPortPos[25] = "-3 0 0";
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logicPortDir[25] = 3;
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logicPortUIName[25] = "In25";
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logicPortType[26] = 1;
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logicPortPos[26] = "-5 0 0";
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logicPortDir[26] = 3;
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logicPortUIName[26] = "In26";
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logicPortType[27] = 1;
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logicPortPos[27] = "-7 0 0";
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logicPortDir[27] = 3;
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logicPortUIName[27] = "In27";
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logicPortType[28] = 1;
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logicPortPos[28] = "-9 0 0";
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logicPortDir[28] = 3;
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logicPortUIName[28] = "In28";
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logicPortType[29] = 1;
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logicPortPos[29] = "-11 0 0";
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logicPortDir[29] = 3;
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logicPortUIName[29] = "In29";
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logicPortType[30] = 1;
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logicPortPos[30] = "-13 0 0";
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logicPortDir[30] = 3;
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logicPortUIName[30] = "In30";
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logicPortType[31] = 1;
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logicPortPos[31] = "-15 0 0";
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logicPortDir[31] = 3;
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logicPortUIName[31] = "In31";
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logicPortType[32] = 1;
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logicPortPos[32] = "-17 0 0";
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logicPortDir[32] = 3;
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logicPortUIName[32] = "In32";
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logicPortType[33] = 1;
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logicPortPos[33] = "-19 0 0";
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logicPortDir[33] = 3;
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logicPortUIName[33] = "In33";
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logicPortType[34] = 1;
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logicPortPos[34] = "-21 0 0";
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logicPortDir[34] = 3;
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logicPortUIName[34] = "In34";
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logicPortType[35] = 1;
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logicPortPos[35] = "-23 0 0";
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logicPortDir[35] = 3;
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logicPortUIName[35] = "In35";
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logicPortType[36] = 1;
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logicPortPos[36] = "-25 0 0";
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logicPortDir[36] = 3;
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logicPortUIName[36] = "In36";
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logicPortType[37] = 1;
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logicPortPos[37] = "-27 0 0";
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logicPortDir[37] = 3;
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logicPortUIName[37] = "In37";
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logicPortType[38] = 1;
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logicPortPos[38] = "-29 0 0";
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logicPortDir[38] = 3;
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logicPortUIName[38] = "In38";
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logicPortType[39] = 1;
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logicPortPos[39] = "-31 0 0";
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logicPortDir[39] = 3;
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logicPortUIName[39] = "In39";
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logicPortType[40] = 1;
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logicPortPos[40] = "-33 0 0";
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logicPortDir[40] = 3;
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logicPortUIName[40] = "In40";
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logicPortType[41] = 1;
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logicPortPos[41] = "-35 0 0";
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logicPortDir[41] = 3;
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logicPortUIName[41] = "In41";
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logicPortType[42] = 1;
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logicPortPos[42] = "-37 0 0";
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logicPortDir[42] = 3;
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logicPortUIName[42] = "In42";
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logicPortType[43] = 1;
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logicPortPos[43] = "-39 0 0";
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logicPortDir[43] = 3;
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logicPortUIName[43] = "In43";
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logicPortType[44] = 1;
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logicPortPos[44] = "-41 0 0";
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logicPortDir[44] = 3;
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logicPortUIName[44] = "In44";
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logicPortType[45] = 1;
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logicPortPos[45] = "-43 0 0";
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logicPortDir[45] = 3;
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logicPortUIName[45] = "In45";
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logicPortType[46] = 1;
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logicPortPos[46] = "-45 0 0";
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logicPortDir[46] = 3;
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logicPortUIName[46] = "In46";
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logicPortType[47] = 1;
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logicPortPos[47] = "-47 0 0";
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logicPortDir[47] = 3;
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logicPortUIName[47] = "In47";
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logicPortType[48] = 0;
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logicPortPos[48] = "47 0 0";
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logicPortDir[48] = 1;
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logicPortUIName[48] = "Out0";
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||||
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logicPortType[49] = 0;
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||||
logicPortPos[49] = "45 0 0";
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logicPortDir[49] = 1;
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logicPortUIName[49] = "Out1";
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logicPortType[50] = 0;
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logicPortPos[50] = "43 0 0";
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logicPortDir[50] = 1;
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logicPortUIName[50] = "Out2";
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logicPortType[51] = 0;
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logicPortPos[51] = "41 0 0";
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logicPortDir[51] = 1;
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logicPortUIName[51] = "Out3";
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||||
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logicPortType[52] = 0;
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||||
logicPortPos[52] = "39 0 0";
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||||
logicPortDir[52] = 1;
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||||
logicPortUIName[52] = "Out4";
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||||
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logicPortType[53] = 0;
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||||
logicPortPos[53] = "37 0 0";
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||||
logicPortDir[53] = 1;
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||||
logicPortUIName[53] = "Out5";
|
||||
|
||||
logicPortType[54] = 0;
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||||
logicPortPos[54] = "35 0 0";
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||||
logicPortDir[54] = 1;
|
||||
logicPortUIName[54] = "Out6";
|
||||
|
||||
logicPortType[55] = 0;
|
||||
logicPortPos[55] = "33 0 0";
|
||||
logicPortDir[55] = 1;
|
||||
logicPortUIName[55] = "Out7";
|
||||
|
||||
logicPortType[56] = 0;
|
||||
logicPortPos[56] = "31 0 0";
|
||||
logicPortDir[56] = 1;
|
||||
logicPortUIName[56] = "Out8";
|
||||
|
||||
logicPortType[57] = 0;
|
||||
logicPortPos[57] = "29 0 0";
|
||||
logicPortDir[57] = 1;
|
||||
logicPortUIName[57] = "Out9";
|
||||
|
||||
logicPortType[58] = 0;
|
||||
logicPortPos[58] = "27 0 0";
|
||||
logicPortDir[58] = 1;
|
||||
logicPortUIName[58] = "Out10";
|
||||
|
||||
logicPortType[59] = 0;
|
||||
logicPortPos[59] = "25 0 0";
|
||||
logicPortDir[59] = 1;
|
||||
logicPortUIName[59] = "Out11";
|
||||
|
||||
logicPortType[60] = 0;
|
||||
logicPortPos[60] = "23 0 0";
|
||||
logicPortDir[60] = 1;
|
||||
logicPortUIName[60] = "Out12";
|
||||
|
||||
logicPortType[61] = 0;
|
||||
logicPortPos[61] = "21 0 0";
|
||||
logicPortDir[61] = 1;
|
||||
logicPortUIName[61] = "Out13";
|
||||
|
||||
logicPortType[62] = 0;
|
||||
logicPortPos[62] = "19 0 0";
|
||||
logicPortDir[62] = 1;
|
||||
logicPortUIName[62] = "Out14";
|
||||
|
||||
logicPortType[63] = 0;
|
||||
logicPortPos[63] = "17 0 0";
|
||||
logicPortDir[63] = 1;
|
||||
logicPortUIName[63] = "Out15";
|
||||
|
||||
logicPortType[64] = 0;
|
||||
logicPortPos[64] = "15 0 0";
|
||||
logicPortDir[64] = 1;
|
||||
logicPortUIName[64] = "Out16";
|
||||
|
||||
logicPortType[65] = 0;
|
||||
logicPortPos[65] = "13 0 0";
|
||||
logicPortDir[65] = 1;
|
||||
logicPortUIName[65] = "Out17";
|
||||
|
||||
logicPortType[66] = 0;
|
||||
logicPortPos[66] = "11 0 0";
|
||||
logicPortDir[66] = 1;
|
||||
logicPortUIName[66] = "Out18";
|
||||
|
||||
logicPortType[67] = 0;
|
||||
logicPortPos[67] = "9 0 0";
|
||||
logicPortDir[67] = 1;
|
||||
logicPortUIName[67] = "Out19";
|
||||
|
||||
logicPortType[68] = 0;
|
||||
logicPortPos[68] = "7 0 0";
|
||||
logicPortDir[68] = 1;
|
||||
logicPortUIName[68] = "Out20";
|
||||
|
||||
logicPortType[69] = 0;
|
||||
logicPortPos[69] = "5 0 0";
|
||||
logicPortDir[69] = 1;
|
||||
logicPortUIName[69] = "Out21";
|
||||
|
||||
logicPortType[70] = 0;
|
||||
logicPortPos[70] = "3 0 0";
|
||||
logicPortDir[70] = 1;
|
||||
logicPortUIName[70] = "Out22";
|
||||
|
||||
logicPortType[71] = 0;
|
||||
logicPortPos[71] = "1 0 0";
|
||||
logicPortDir[71] = 1;
|
||||
logicPortUIName[71] = "Out23";
|
||||
|
||||
logicPortType[72] = 0;
|
||||
logicPortPos[72] = "-1 0 0";
|
||||
logicPortDir[72] = 1;
|
||||
logicPortUIName[72] = "Out24";
|
||||
|
||||
logicPortType[73] = 0;
|
||||
logicPortPos[73] = "-3 0 0";
|
||||
logicPortDir[73] = 1;
|
||||
logicPortUIName[73] = "Out25";
|
||||
|
||||
logicPortType[74] = 0;
|
||||
logicPortPos[74] = "-5 0 0";
|
||||
logicPortDir[74] = 1;
|
||||
logicPortUIName[74] = "Out26";
|
||||
|
||||
logicPortType[75] = 0;
|
||||
logicPortPos[75] = "-7 0 0";
|
||||
logicPortDir[75] = 1;
|
||||
logicPortUIName[75] = "Out27";
|
||||
|
||||
logicPortType[76] = 0;
|
||||
logicPortPos[76] = "-9 0 0";
|
||||
logicPortDir[76] = 1;
|
||||
logicPortUIName[76] = "Out28";
|
||||
|
||||
logicPortType[77] = 0;
|
||||
logicPortPos[77] = "-11 0 0";
|
||||
logicPortDir[77] = 1;
|
||||
logicPortUIName[77] = "Out29";
|
||||
|
||||
logicPortType[78] = 0;
|
||||
logicPortPos[78] = "-13 0 0";
|
||||
logicPortDir[78] = 1;
|
||||
logicPortUIName[78] = "Out30";
|
||||
|
||||
logicPortType[79] = 0;
|
||||
logicPortPos[79] = "-15 0 0";
|
||||
logicPortDir[79] = 1;
|
||||
logicPortUIName[79] = "Out31";
|
||||
|
||||
logicPortType[80] = 0;
|
||||
logicPortPos[80] = "-17 0 0";
|
||||
logicPortDir[80] = 1;
|
||||
logicPortUIName[80] = "Out32";
|
||||
|
||||
logicPortType[81] = 0;
|
||||
logicPortPos[81] = "-19 0 0";
|
||||
logicPortDir[81] = 1;
|
||||
logicPortUIName[81] = "Out33";
|
||||
|
||||
logicPortType[82] = 0;
|
||||
logicPortPos[82] = "-21 0 0";
|
||||
logicPortDir[82] = 1;
|
||||
logicPortUIName[82] = "Out34";
|
||||
|
||||
logicPortType[83] = 0;
|
||||
logicPortPos[83] = "-23 0 0";
|
||||
logicPortDir[83] = 1;
|
||||
logicPortUIName[83] = "Out35";
|
||||
|
||||
logicPortType[84] = 0;
|
||||
logicPortPos[84] = "-25 0 0";
|
||||
logicPortDir[84] = 1;
|
||||
logicPortUIName[84] = "Out36";
|
||||
|
||||
logicPortType[85] = 0;
|
||||
logicPortPos[85] = "-27 0 0";
|
||||
logicPortDir[85] = 1;
|
||||
logicPortUIName[85] = "Out37";
|
||||
|
||||
logicPortType[86] = 0;
|
||||
logicPortPos[86] = "-29 0 0";
|
||||
logicPortDir[86] = 1;
|
||||
logicPortUIName[86] = "Out38";
|
||||
|
||||
logicPortType[87] = 0;
|
||||
logicPortPos[87] = "-31 0 0";
|
||||
logicPortDir[87] = 1;
|
||||
logicPortUIName[87] = "Out39";
|
||||
|
||||
logicPortType[88] = 0;
|
||||
logicPortPos[88] = "-33 0 0";
|
||||
logicPortDir[88] = 1;
|
||||
logicPortUIName[88] = "Out40";
|
||||
|
||||
logicPortType[89] = 0;
|
||||
logicPortPos[89] = "-35 0 0";
|
||||
logicPortDir[89] = 1;
|
||||
logicPortUIName[89] = "Out41";
|
||||
|
||||
logicPortType[90] = 0;
|
||||
logicPortPos[90] = "-37 0 0";
|
||||
logicPortDir[90] = 1;
|
||||
logicPortUIName[90] = "Out42";
|
||||
|
||||
logicPortType[91] = 0;
|
||||
logicPortPos[91] = "-39 0 0";
|
||||
logicPortDir[91] = 1;
|
||||
logicPortUIName[91] = "Out43";
|
||||
|
||||
logicPortType[92] = 0;
|
||||
logicPortPos[92] = "-41 0 0";
|
||||
logicPortDir[92] = 1;
|
||||
logicPortUIName[92] = "Out44";
|
||||
|
||||
logicPortType[93] = 0;
|
||||
logicPortPos[93] = "-43 0 0";
|
||||
logicPortDir[93] = 1;
|
||||
logicPortUIName[93] = "Out45";
|
||||
|
||||
logicPortType[94] = 0;
|
||||
logicPortPos[94] = "-45 0 0";
|
||||
logicPortDir[94] = 1;
|
||||
logicPortUIName[94] = "Out46";
|
||||
|
||||
logicPortType[95] = 0;
|
||||
logicPortPos[95] = "-47 0 0";
|
||||
logicPortDir[95] = 1;
|
||||
logicPortUIName[95] = "Out47";
|
||||
|
||||
logicPortType[96] = 1;
|
||||
logicPortPos[96] = "47 0 0";
|
||||
logicPortDir[96] = 2;
|
||||
logicPortUIName[96] = "Clock";
|
||||
logicPortCauseUpdate[96] = true;
|
||||
|
||||
};
|
||||
Reference in New Issue
Block a user