redo/Brick_LuaLogic
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more wires, fix rom

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Redo0
2021-07-24 15:32:14 -05:00
parent 4501eea02e
commit 519a887dca
30 changed files with 171 additions and 80 deletions
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9
bricks/gen/newcode/ROM 16x8.cs
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@@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom16x8_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 9) then " @
" if Gate.getportstate(gate, 9)~=0 then " @
" Gate.setportstate(gate, 8, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@@ -66,43 +66,36 @@ datablock fxDtsBrickData(LogicGate_Rom16x8_Data){
logicPortPos[0] = "15 -7 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "13 -7 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "11 -7 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "9 -7 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "7 -7 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "5 -7 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "3 -7 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 0;
logicPortPos[7] = "15 7 0";