redo/Brick_LuaLogic
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more wires, fix rom

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Redo0
2021-07-24 15:32:14 -05:00
parent 4501eea02e
commit 519a887dca
30 changed files with 171 additions and 80 deletions
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12
bricks/gen/newcode/ROM 32x32.cs
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@@ -39,7 +39,7 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
;
logicUpdate =
"return function(gate) " @
" if Gate.getportstate(gate, 12) then " @
" if Gate.getportstate(gate, 12)~=0 then " @
" Gate.setportstate(gate, 11, gate.romdata[( " @
" (Gate.getportstate(gate, 1)) " @
" + (Gate.getportstate(gate, 2) * 2) " @
@@ -69,61 +69,51 @@ datablock fxDtsBrickData(LogicGate_Rom32x32_Data){
logicPortPos[0] = "31 -31 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortCauseUpdate[0] = true;
logicPortType[1] = 1;
logicPortPos[1] = "29 -31 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortCauseUpdate[1] = true;
logicPortType[2] = 1;
logicPortPos[2] = "27 -31 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortCauseUpdate[2] = true;
logicPortType[3] = 1;
logicPortPos[3] = "25 -31 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortCauseUpdate[3] = true;
logicPortType[4] = 1;
logicPortPos[4] = "23 -31 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortCauseUpdate[4] = true;
logicPortType[5] = 1;
logicPortPos[5] = "21 -31 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortCauseUpdate[5] = true;
logicPortType[6] = 1;
logicPortPos[6] = "19 -31 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortCauseUpdate[6] = true;
logicPortType[7] = 1;
logicPortPos[7] = "17 -31 0";
logicPortDir[7] = 3;
logicPortUIName[7] = "Addr7";
logicPortCauseUpdate[7] = true;
logicPortType[8] = 1;
logicPortPos[8] = "15 -31 0";
logicPortDir[8] = 3;
logicPortUIName[8] = "Addr8";
logicPortCauseUpdate[8] = true;
logicPortType[9] = 1;
logicPortPos[9] = "13 -31 0";
logicPortDir[9] = 3;
logicPortUIName[9] = "Addr9";
logicPortCauseUpdate[9] = true;
logicPortType[10] = 0;
logicPortPos[10] = "31 31 0";