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remove active low buses; add vertical gates and more rom sizes

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Redo0
2021-05-28 22:12:55 -05:00
parent 95164ab7bf
commit b08c3cd0c4
1279 changed files with 38991 additions and 688490 deletions
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31
bricks/gen/newcode/ROM 16x16.cs
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@@ -39,20 +39,25 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
;
logicUpdate =
"return function(gate) " @
" local addr = (Gate.getportstate(gate, 1) and 1 or 0) " @
" + (Gate.getportstate(gate, 2) and 2 or 0) " @
" + (Gate.getportstate(gate, 3) and 4 or 0) " @
" + (Gate.getportstate(gate, 4) and 8 or 0) " @
" + (Gate.getportstate(gate, 5) and 16 or 0) " @
" + (Gate.getportstate(gate, 6) and 32 or 0) " @
" + (Gate.getportstate(gate, 7) and 64 or 0) " @
" + (Gate.getportstate(gate, 8) and 128 or 0) " @
" Gate.setportstate(gate, 9, gate.romdata[addr]) " @
" if Gate.getportstate(gate, 10) then " @
" Gate.setportstate(gate, 9, gate.romdata[( " @
" (Gate.getportstate(gate, 1) and 1 or 0) " @
" + (Gate.getportstate(gate, 2) and 2 or 0) " @
" + (Gate.getportstate(gate, 3) and 4 or 0) " @
" + (Gate.getportstate(gate, 4) and 8 or 0) " @
" + (Gate.getportstate(gate, 5) and 16 or 0) " @
" + (Gate.getportstate(gate, 6) and 32 or 0) " @
" + (Gate.getportstate(gate, 7) and 64 or 0) " @
" + (Gate.getportstate(gate, 8) and 128 or 0) " @
" )]) " @
" else " @
" Gate.setportstate(gate, 9, false) " @
" end " @
"end"
;
logicGlobal = "";
numLogicPorts = 9;
numLogicPorts = 10;
isLogicRom = true;
logicRomY = 16;
@@ -111,6 +116,12 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
logicPortDir[8] = 1;
logicPortUIName[8] = "Out";
logicPortType[9] = 1;
logicPortPos[9] = "15 -15 0";
logicPortDir[9] = 2;
logicPortUIName[9] = "In";
logicPortCauseUpdate[9] = true;
};
function LogicGate_Rom16x16_Data::Logic_onAdd(%data, %brick) {