add math gates

2025-01-13 01:59:24 -07:00
parent 38ad0d3058
commit bfe8012e3c
69 changed files with 75334 additions and 0 deletions
--- a/bricks/gen/newcode/Divider
+++ b/bricks/gen/newcode/Divider
@@ -0,0 +1,207 @@
+
+datablock fxDtsBrickData(LogicGate_Divider8Bit_Data){
+	brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Multiplier 8 Bit.blb";
+	iconName = $LuaLogic::Path @ "bricks/gen/newicons/Multiplier 8 Bit";
+	
+	category = "Logic Bricks";
+	subCategory = "Math";
+	uiName = "Divider 8 Bit";
+	logicUIName = "Divider 8 Bit";
+	logicUIDesc = "";
+	
+	hasPrint = 1;
+	printAspectRatio = "Logic";
+	
+	logicBrickSize = "16 2 1";
+	orientationFix = 3;
+	
+	isLogic = true;
+	isLogicGate = true;
+	isLogicInput = false;
+	
+	logicInit = "";
+	logicInput = "";
+	logicUpdate = "";
+	logicGlobal = "";
+	
+	numLogicPorts = 32;
+	
+	
+	
+	logicPortType[0] = 1;
+	logicPortPos[0] = "15 -1 0";
+	logicPortDir[0] = 3;
+	logicPortUIName[0] = "A0";
+	logicPortCauseUpdate[0] = true;
+	
+	logicPortType[1] = 1;
+	logicPortPos[1] = "13 -1 0";
+	logicPortDir[1] = 3;
+	logicPortUIName[1] = "A1";
+	logicPortCauseUpdate[1] = true;
+	
+	logicPortType[2] = 1;
+	logicPortPos[2] = "11 -1 0";
+	logicPortDir[2] = 3;
+	logicPortUIName[2] = "A2";
+	logicPortCauseUpdate[2] = true;
+	
+	logicPortType[3] = 1;
+	logicPortPos[3] = "9 -1 0";
+	logicPortDir[3] = 3;
+	logicPortUIName[3] = "A3";
+	logicPortCauseUpdate[3] = true;
+	
+	logicPortType[4] = 1;
+	logicPortPos[4] = "7 -1 0";
+	logicPortDir[4] = 3;
+	logicPortUIName[4] = "A4";
+	logicPortCauseUpdate[4] = true;
+	
+	logicPortType[5] = 1;
+	logicPortPos[5] = "5 -1 0";
+	logicPortDir[5] = 3;
+	logicPortUIName[5] = "A5";
+	logicPortCauseUpdate[5] = true;
+	
+	logicPortType[6] = 1;
+	logicPortPos[6] = "3 -1 0";
+	logicPortDir[6] = 3;
+	logicPortUIName[6] = "A6";
+	logicPortCauseUpdate[6] = true;
+	
+	logicPortType[7] = 1;
+	logicPortPos[7] = "1 -1 0";
+	logicPortDir[7] = 3;
+	logicPortUIName[7] = "A7";
+	logicPortCauseUpdate[7] = true;
+	
+	logicPortType[8] = 1;
+	logicPortPos[8] = "-1 -1 0";
+	logicPortDir[8] = 3;
+	logicPortUIName[8] = "B0";
+	logicPortCauseUpdate[8] = true;
+	
+	logicPortType[9] = 1;
+	logicPortPos[9] = "-3 -1 0";
+	logicPortDir[9] = 3;
+	logicPortUIName[9] = "B1";
+	logicPortCauseUpdate[9] = true;
+	
+	logicPortType[10] = 1;
+	logicPortPos[10] = "-5 -1 0";
+	logicPortDir[10] = 3;
+	logicPortUIName[10] = "B2";
+	logicPortCauseUpdate[10] = true;
+	
+	logicPortType[11] = 1;
+	logicPortPos[11] = "-7 -1 0";
+	logicPortDir[11] = 3;
+	logicPortUIName[11] = "B3";
+	logicPortCauseUpdate[11] = true;
+	
+	logicPortType[12] = 1;
+	logicPortPos[12] = "-9 -1 0";
+	logicPortDir[12] = 3;
+	logicPortUIName[12] = "B4";
+	logicPortCauseUpdate[12] = true;
+	
+	logicPortType[13] = 1;
+	logicPortPos[13] = "-11 -1 0";
+	logicPortDir[13] = 3;
+	logicPortUIName[13] = "B5";
+	logicPortCauseUpdate[13] = true;
+	
+	logicPortType[14] = 1;
+	logicPortPos[14] = "-13 -1 0";
+	logicPortDir[14] = 3;
+	logicPortUIName[14] = "B6";
+	logicPortCauseUpdate[14] = true;
+	
+	logicPortType[15] = 1;
+	logicPortPos[15] = "-15 -1 0";
+	logicPortDir[15] = 3;
+	logicPortUIName[15] = "B7";
+	logicPortCauseUpdate[15] = true;
+	
+	logicPortType[16] = 0;
+	logicPortPos[16] = "15 1 0";
+	logicPortDir[16] = 1;
+	logicPortUIName[16] = "Q0";
+	
+	logicPortType[17] = 0;
+	logicPortPos[17] = "13 1 0";
+	logicPortDir[17] = 1;
+	logicPortUIName[17] = "Q1";
+	
+	logicPortType[18] = 0;
+	logicPortPos[18] = "11 1 0";
+	logicPortDir[18] = 1;
+	logicPortUIName[18] = "Q2";
+	
+	logicPortType[19] = 0;
+	logicPortPos[19] = "9 1 0";
+	logicPortDir[19] = 1;
+	logicPortUIName[19] = "Q3";
+	
+	logicPortType[20] = 0;
+	logicPortPos[20] = "7 1 0";
+	logicPortDir[20] = 1;
+	logicPortUIName[20] = "Q4";
+	
+	logicPortType[21] = 0;
+	logicPortPos[21] = "5 1 0";
+	logicPortDir[21] = 1;
+	logicPortUIName[21] = "Q5";
+	
+	logicPortType[22] = 0;
+	logicPortPos[22] = "3 1 0";
+	logicPortDir[22] = 1;
+	logicPortUIName[22] = "Q6";
+	
+	logicPortType[23] = 0;
+	logicPortPos[23] = "1 1 0";
+	logicPortDir[23] = 1;
+	logicPortUIName[23] = "Q7";
+	
+	logicPortType[24] = 0;
+	logicPortPos[24] = "-1 1 0";
+	logicPortDir[24] = 1;
+	logicPortUIName[24] = "R0";
+	
+	logicPortType[25] = 0;
+	logicPortPos[25] = "-3 1 0";
+	logicPortDir[25] = 1;
+	logicPortUIName[25] = "R1";
+	
+	logicPortType[26] = 0;
+	logicPortPos[26] = "-5 1 0";
+	logicPortDir[26] = 1;
+	logicPortUIName[26] = "R2";
+	
+	logicPortType[27] = 0;
+	logicPortPos[27] = "-7 1 0";
+	logicPortDir[27] = 1;
+	logicPortUIName[27] = "R3";
+	
+	logicPortType[28] = 0;
+	logicPortPos[28] = "-9 1 0";
+	logicPortDir[28] = 1;
+	logicPortUIName[28] = "R4";
+	
+	logicPortType[29] = 0;
+	logicPortPos[29] = "-11 1 0";
+	logicPortDir[29] = 1;
+	logicPortUIName[29] = "R5";
+	
+	logicPortType[30] = 0;
+	logicPortPos[30] = "-13 1 0";
+	logicPortDir[30] = 1;
+	logicPortUIName[30] = "R6";
+	
+	logicPortType[31] = 0;
+	logicPortPos[31] = "-15 1 0";
+	logicPortDir[31] = 1;
+	logicPortUIName[31] = "R7";
+	
+};