add vertical bus bricks; delete redundant diode bricks
This commit is contained in:
175
bricks/gen/newcode/Buffer 11 Bit Down.cs
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175
bricks/gen/newcode/Buffer 11 Bit Down.cs
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@@ -0,0 +1,175 @@
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datablock fxDtsBrickData(Buffer11BitDown){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Buffer 11 Bit Down.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Buffer 11 Bit Down";
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category = "Logic Bricks";
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subCategory = "Bus";
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uiName = "Buffer 11 Bit Down";
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logicUIName = "Buffer 11 Bit Down";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "11 1 1";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 23) then " @
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" Gate.setportstate(gate, 12, Gate.getportstate(gate, 1)) " @
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" Gate.setportstate(gate, 13, Gate.getportstate(gate, 2)) " @
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" Gate.setportstate(gate, 14, Gate.getportstate(gate, 3)) " @
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" Gate.setportstate(gate, 15, Gate.getportstate(gate, 4)) " @
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" Gate.setportstate(gate, 16, Gate.getportstate(gate, 5)) " @
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" Gate.setportstate(gate, 17, Gate.getportstate(gate, 6)) " @
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" Gate.setportstate(gate, 18, Gate.getportstate(gate, 7)) " @
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" Gate.setportstate(gate, 19, Gate.getportstate(gate, 8)) " @
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" Gate.setportstate(gate, 20, Gate.getportstate(gate, 9)) " @
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" Gate.setportstate(gate, 21, Gate.getportstate(gate, 10)) " @
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" Gate.setportstate(gate, 22, Gate.getportstate(gate, 11)) " @
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" else " @
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" Gate.setportstate(gate, 12, false) " @
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" Gate.setportstate(gate, 13, false) " @
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" Gate.setportstate(gate, 14, false) " @
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" Gate.setportstate(gate, 15, false) " @
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" Gate.setportstate(gate, 16, false) " @
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" Gate.setportstate(gate, 17, false) " @
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" Gate.setportstate(gate, 18, false) " @
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" Gate.setportstate(gate, 19, false) " @
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" Gate.setportstate(gate, 20, false) " @
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" Gate.setportstate(gate, 21, false) " @
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" Gate.setportstate(gate, 22, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 23;
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logicPortType[0] = 1;
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logicPortPos[0] = "10 0 0";
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logicPortDir[0] = 4;
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logicPortUIName[0] = "In0";
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logicPortType[1] = 1;
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logicPortPos[1] = "8 0 0";
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logicPortDir[1] = 4;
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logicPortUIName[1] = "In1";
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logicPortType[2] = 1;
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logicPortPos[2] = "6 0 0";
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logicPortDir[2] = 4;
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logicPortUIName[2] = "In2";
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logicPortType[3] = 1;
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logicPortPos[3] = "4 0 0";
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logicPortDir[3] = 4;
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logicPortUIName[3] = "In3";
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logicPortType[4] = 1;
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logicPortPos[4] = "2 0 0";
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logicPortDir[4] = 4;
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logicPortUIName[4] = "In4";
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logicPortType[5] = 1;
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logicPortPos[5] = "0 0 0";
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logicPortDir[5] = 4;
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logicPortUIName[5] = "In5";
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logicPortType[6] = 1;
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logicPortPos[6] = "-2 0 0";
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logicPortDir[6] = 4;
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logicPortUIName[6] = "In6";
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logicPortType[7] = 1;
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logicPortPos[7] = "-4 0 0";
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logicPortDir[7] = 4;
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logicPortUIName[7] = "In7";
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logicPortType[8] = 1;
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logicPortPos[8] = "-6 0 0";
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logicPortDir[8] = 4;
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logicPortUIName[8] = "In8";
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logicPortType[9] = 1;
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logicPortPos[9] = "-8 0 0";
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logicPortDir[9] = 4;
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logicPortUIName[9] = "In9";
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logicPortType[10] = 1;
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logicPortPos[10] = "-10 0 0";
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logicPortDir[10] = 4;
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logicPortUIName[10] = "In10";
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logicPortType[11] = 0;
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logicPortPos[11] = "10 0 0";
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logicPortDir[11] = 5;
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logicPortUIName[11] = "Out0";
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logicPortType[12] = 0;
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logicPortPos[12] = "8 0 0";
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logicPortDir[12] = 5;
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logicPortUIName[12] = "Out1";
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logicPortType[13] = 0;
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logicPortPos[13] = "6 0 0";
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logicPortDir[13] = 5;
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logicPortUIName[13] = "Out2";
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logicPortType[14] = 0;
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logicPortPos[14] = "4 0 0";
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logicPortDir[14] = 5;
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logicPortUIName[14] = "Out3";
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logicPortType[15] = 0;
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logicPortPos[15] = "2 0 0";
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logicPortDir[15] = 5;
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logicPortUIName[15] = "Out4";
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logicPortType[16] = 0;
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logicPortPos[16] = "0 0 0";
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logicPortDir[16] = 5;
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logicPortUIName[16] = "Out5";
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logicPortType[17] = 0;
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logicPortPos[17] = "-2 0 0";
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logicPortDir[17] = 5;
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logicPortUIName[17] = "Out6";
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logicPortType[18] = 0;
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logicPortPos[18] = "-4 0 0";
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logicPortDir[18] = 5;
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logicPortUIName[18] = "Out7";
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logicPortType[19] = 0;
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logicPortPos[19] = "-6 0 0";
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logicPortDir[19] = 5;
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logicPortUIName[19] = "Out8";
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logicPortType[20] = 0;
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logicPortPos[20] = "-8 0 0";
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logicPortDir[20] = 5;
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logicPortUIName[20] = "Out9";
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logicPortType[21] = 0;
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logicPortPos[21] = "-10 0 0";
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logicPortDir[21] = 5;
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logicPortUIName[21] = "Out10";
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logicPortType[22] = 1;
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logicPortPos[22] = "10 0 0";
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logicPortDir[22] = 2;
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logicPortUIName[22] = "Clock";
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logicPortCauseUpdate[22] = true;
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};
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