add vertical bus bricks; delete redundant diode bricks

2021-05-22 17:58:13 -05:00
parent de586ff608
commit ce07ef3263
1041 changed files with 965928 additions and 1235 deletions
--- a/bricks/gen/newcode/Mux
+++ b/bricks/gen/newcode/Mux
@@ -0,0 +1,120 @@
+
+datablock fxDtsBrickData(LogicGate_Mux3Vertical_Data){
+	brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Mux 3 Bit Vertical.blb";
+	iconName = $LuaLogic::Path @ "bricks/gen/newicons/Mux 3 Bit Vertical";
+	
+	category = "Logic Bricks";
+	subCategory = "Mux";
+	uiName = "Mux 3 Bit Vertical";
+	logicUIName = "Mux 3 Bit Vertical";
+	logicUIDesc = "";
+	
+	hasPrint = 1;
+	printAspectRatio = "Logic";
+	
+	logicBrickSize = "1 1 8";
+	orientationFix = 3;
+	
+	isLogic = true;
+	isLogicGate = true;
+	isLogicInput = false;
+	
+	logicInit = "";
+	logicInput = "";
+	logicUpdate = 
+		"return function(gate) " @
+		"	if Gate.getportstate(gate, 12) then " @
+		"		local idx = 4 + " @
+		"			(bool_to_int[Gate.getportstate(gate, 1)] * 1) + " @
+		"			(bool_to_int[Gate.getportstate(gate, 2)] * 2) + " @
+		"			(bool_to_int[Gate.getportstate(gate, 3)] * 4) " @
+		"		Gate.setportstate(gate, 13, Gate.getportstate(gate, idx)) " @
+		"	else " @
+		"		Gate.setportstate(gate, 13, false) " @
+		"	end " @
+		"end"
+	;
+	logicGlobal = "";
+	
+	numLogicPorts = 13;
+	
+	
+	
+	logicPortType[0] = 1;
+	logicPortPos[0] = "0 0 -7";
+	logicPortDir[0] = 3;
+	logicPortUIName[0] = "Sel0";
+	logicPortCauseUpdate[0] = true;
+	
+	logicPortType[1] = 1;
+	logicPortPos[1] = "0 0 -5";
+	logicPortDir[1] = 3;
+	logicPortUIName[1] = "Sel1";
+	logicPortCauseUpdate[1] = true;
+	
+	logicPortType[2] = 1;
+	logicPortPos[2] = "0 0 -3";
+	logicPortDir[2] = 3;
+	logicPortUIName[2] = "Sel2";
+	logicPortCauseUpdate[2] = true;
+	
+	logicPortType[3] = 1;
+	logicPortPos[3] = "0 0 -7";
+	logicPortDir[3] = 1;
+	logicPortUIName[3] = "In0";
+	logicPortCauseUpdate[3] = true;
+	
+	logicPortType[4] = 1;
+	logicPortPos[4] = "0 0 -5";
+	logicPortDir[4] = 1;
+	logicPortUIName[4] = "In1";
+	logicPortCauseUpdate[4] = true;
+	
+	logicPortType[5] = 1;
+	logicPortPos[5] = "0 0 -3";
+	logicPortDir[5] = 1;
+	logicPortUIName[5] = "In2";
+	logicPortCauseUpdate[5] = true;
+	
+	logicPortType[6] = 1;
+	logicPortPos[6] = "0 0 -1";
+	logicPortDir[6] = 1;
+	logicPortUIName[6] = "In3";
+	logicPortCauseUpdate[6] = true;
+	
+	logicPortType[7] = 1;
+	logicPortPos[7] = "0 0 1";
+	logicPortDir[7] = 1;
+	logicPortUIName[7] = "In4";
+	logicPortCauseUpdate[7] = true;
+	
+	logicPortType[8] = 1;
+	logicPortPos[8] = "0 0 3";
+	logicPortDir[8] = 1;
+	logicPortUIName[8] = "In5";
+	logicPortCauseUpdate[8] = true;
+	
+	logicPortType[9] = 1;
+	logicPortPos[9] = "0 0 5";
+	logicPortDir[9] = 1;
+	logicPortUIName[9] = "In6";
+	logicPortCauseUpdate[9] = true;
+	
+	logicPortType[10] = 1;
+	logicPortPos[10] = "0 0 7";
+	logicPortDir[10] = 1;
+	logicPortUIName[10] = "In7";
+	logicPortCauseUpdate[10] = true;
+	
+	logicPortType[11] = 1;
+	logicPortPos[11] = "0 0 -7";
+	logicPortDir[11] = 5;
+	logicPortUIName[11] = "Enable";
+	logicPortCauseUpdate[11] = true;
+	
+	logicPortType[12] = 0;
+	logicPortPos[12] = "0 0 7";
+	logicPortDir[12] = 4;
+	logicPortUIName[12] = "Out";
+	
+};