add vertical bus bricks; delete redundant diode bricks
This commit is contained in:
278
bricks/gen/newcode/Mux 5 Bit Vertical.cs
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278
bricks/gen/newcode/Mux 5 Bit Vertical.cs
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@@ -0,0 +1,278 @@
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datablock fxDtsBrickData(LogicGate_Mux5Vertical_Data){
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brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/Mux 5 Bit Vertical.blb";
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iconName = $LuaLogic::Path @ "bricks/gen/newicons/Mux 5 Bit Vertical";
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category = "Logic Bricks";
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subCategory = "Mux";
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uiName = "Mux 5 Bit Vertical";
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logicUIName = "Mux 5 Bit Vertical";
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logicUIDesc = "";
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hasPrint = 1;
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printAspectRatio = "Logic";
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logicBrickSize = "1 1 32";
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orientationFix = 3;
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isLogic = true;
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isLogicGate = true;
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isLogicInput = false;
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logicInit = "";
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logicInput = "";
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logicUpdate =
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"return function(gate) " @
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" if Gate.getportstate(gate, 38) then " @
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" local idx = 6 + " @
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" (bool_to_int[Gate.getportstate(gate, 1)] * 1) + " @
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" (bool_to_int[Gate.getportstate(gate, 2)] * 2) + " @
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" (bool_to_int[Gate.getportstate(gate, 3)] * 4) + " @
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" (bool_to_int[Gate.getportstate(gate, 4)] * 8) + " @
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" (bool_to_int[Gate.getportstate(gate, 5)] * 16) " @
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" Gate.setportstate(gate, 39, Gate.getportstate(gate, idx)) " @
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" else " @
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" Gate.setportstate(gate, 39, false) " @
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" end " @
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"end"
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;
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logicGlobal = "";
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numLogicPorts = 39;
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logicPortType[0] = 1;
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logicPortPos[0] = "0 0 -31";
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logicPortDir[0] = 3;
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logicPortUIName[0] = "Sel0";
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logicPortCauseUpdate[0] = true;
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logicPortType[1] = 1;
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logicPortPos[1] = "0 0 -29";
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logicPortDir[1] = 3;
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logicPortUIName[1] = "Sel1";
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logicPortCauseUpdate[1] = true;
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logicPortType[2] = 1;
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logicPortPos[2] = "0 0 -27";
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logicPortDir[2] = 3;
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logicPortUIName[2] = "Sel2";
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logicPortCauseUpdate[2] = true;
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logicPortType[3] = 1;
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logicPortPos[3] = "0 0 -25";
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logicPortDir[3] = 3;
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logicPortUIName[3] = "Sel3";
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logicPortCauseUpdate[3] = true;
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logicPortType[4] = 1;
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logicPortPos[4] = "0 0 -23";
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logicPortDir[4] = 3;
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logicPortUIName[4] = "Sel4";
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logicPortCauseUpdate[4] = true;
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logicPortType[5] = 1;
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logicPortPos[5] = "0 0 -31";
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logicPortDir[5] = 1;
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logicPortUIName[5] = "In0";
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logicPortCauseUpdate[5] = true;
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logicPortType[6] = 1;
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logicPortPos[6] = "0 0 -29";
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logicPortDir[6] = 1;
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logicPortUIName[6] = "In1";
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logicPortCauseUpdate[6] = true;
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logicPortType[7] = 1;
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logicPortPos[7] = "0 0 -27";
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logicPortDir[7] = 1;
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logicPortUIName[7] = "In2";
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logicPortCauseUpdate[7] = true;
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logicPortType[8] = 1;
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logicPortPos[8] = "0 0 -25";
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logicPortDir[8] = 1;
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logicPortUIName[8] = "In3";
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logicPortCauseUpdate[8] = true;
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logicPortType[9] = 1;
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logicPortPos[9] = "0 0 -23";
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logicPortDir[9] = 1;
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logicPortUIName[9] = "In4";
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logicPortCauseUpdate[9] = true;
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logicPortType[10] = 1;
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logicPortPos[10] = "0 0 -21";
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logicPortDir[10] = 1;
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logicPortUIName[10] = "In5";
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logicPortCauseUpdate[10] = true;
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logicPortType[11] = 1;
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logicPortPos[11] = "0 0 -19";
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logicPortDir[11] = 1;
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logicPortUIName[11] = "In6";
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logicPortCauseUpdate[11] = true;
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logicPortType[12] = 1;
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logicPortPos[12] = "0 0 -17";
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logicPortDir[12] = 1;
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logicPortUIName[12] = "In7";
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logicPortCauseUpdate[12] = true;
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logicPortType[13] = 1;
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logicPortPos[13] = "0 0 -15";
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logicPortDir[13] = 1;
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logicPortUIName[13] = "In8";
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logicPortCauseUpdate[13] = true;
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logicPortType[14] = 1;
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logicPortPos[14] = "0 0 -13";
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logicPortDir[14] = 1;
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logicPortUIName[14] = "In9";
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logicPortCauseUpdate[14] = true;
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logicPortType[15] = 1;
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logicPortPos[15] = "0 0 -11";
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logicPortDir[15] = 1;
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logicPortUIName[15] = "In10";
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logicPortCauseUpdate[15] = true;
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logicPortType[16] = 1;
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logicPortPos[16] = "0 0 -9";
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logicPortDir[16] = 1;
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logicPortUIName[16] = "In11";
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logicPortCauseUpdate[16] = true;
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logicPortType[17] = 1;
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logicPortPos[17] = "0 0 -7";
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logicPortDir[17] = 1;
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logicPortUIName[17] = "In12";
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logicPortCauseUpdate[17] = true;
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logicPortType[18] = 1;
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logicPortPos[18] = "0 0 -5";
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logicPortDir[18] = 1;
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logicPortUIName[18] = "In13";
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logicPortCauseUpdate[18] = true;
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logicPortType[19] = 1;
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logicPortPos[19] = "0 0 -3";
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logicPortDir[19] = 1;
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logicPortUIName[19] = "In14";
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logicPortCauseUpdate[19] = true;
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logicPortType[20] = 1;
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logicPortPos[20] = "0 0 -1";
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logicPortDir[20] = 1;
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logicPortUIName[20] = "In15";
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logicPortCauseUpdate[20] = true;
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logicPortType[21] = 1;
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logicPortPos[21] = "0 0 1";
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logicPortDir[21] = 1;
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logicPortUIName[21] = "In16";
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logicPortCauseUpdate[21] = true;
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logicPortType[22] = 1;
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logicPortPos[22] = "0 0 3";
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logicPortDir[22] = 1;
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logicPortUIName[22] = "In17";
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logicPortCauseUpdate[22] = true;
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logicPortType[23] = 1;
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logicPortPos[23] = "0 0 5";
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logicPortDir[23] = 1;
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logicPortUIName[23] = "In18";
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logicPortCauseUpdate[23] = true;
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logicPortType[24] = 1;
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logicPortPos[24] = "0 0 7";
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logicPortDir[24] = 1;
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logicPortUIName[24] = "In19";
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logicPortCauseUpdate[24] = true;
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logicPortType[25] = 1;
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logicPortPos[25] = "0 0 9";
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logicPortDir[25] = 1;
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logicPortUIName[25] = "In20";
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logicPortCauseUpdate[25] = true;
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logicPortType[26] = 1;
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logicPortPos[26] = "0 0 11";
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logicPortDir[26] = 1;
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logicPortUIName[26] = "In21";
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logicPortCauseUpdate[26] = true;
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logicPortType[27] = 1;
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logicPortPos[27] = "0 0 13";
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logicPortDir[27] = 1;
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logicPortUIName[27] = "In22";
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logicPortCauseUpdate[27] = true;
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logicPortType[28] = 1;
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logicPortPos[28] = "0 0 15";
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logicPortDir[28] = 1;
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logicPortUIName[28] = "In23";
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logicPortCauseUpdate[28] = true;
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logicPortType[29] = 1;
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logicPortPos[29] = "0 0 17";
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logicPortDir[29] = 1;
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logicPortUIName[29] = "In24";
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logicPortCauseUpdate[29] = true;
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logicPortType[30] = 1;
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logicPortPos[30] = "0 0 19";
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logicPortDir[30] = 1;
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logicPortUIName[30] = "In25";
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logicPortCauseUpdate[30] = true;
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logicPortType[31] = 1;
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logicPortPos[31] = "0 0 21";
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logicPortDir[31] = 1;
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logicPortUIName[31] = "In26";
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logicPortCauseUpdate[31] = true;
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logicPortType[32] = 1;
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logicPortPos[32] = "0 0 23";
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logicPortDir[32] = 1;
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logicPortUIName[32] = "In27";
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logicPortCauseUpdate[32] = true;
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logicPortType[33] = 1;
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logicPortPos[33] = "0 0 25";
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logicPortDir[33] = 1;
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logicPortUIName[33] = "In28";
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logicPortCauseUpdate[33] = true;
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logicPortType[34] = 1;
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logicPortPos[34] = "0 0 27";
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logicPortDir[34] = 1;
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logicPortUIName[34] = "In29";
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logicPortCauseUpdate[34] = true;
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logicPortType[35] = 1;
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logicPortPos[35] = "0 0 29";
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logicPortDir[35] = 1;
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logicPortUIName[35] = "In30";
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logicPortCauseUpdate[35] = true;
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logicPortType[36] = 1;
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logicPortPos[36] = "0 0 31";
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logicPortDir[36] = 1;
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logicPortUIName[36] = "In31";
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logicPortCauseUpdate[36] = true;
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logicPortType[37] = 1;
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logicPortPos[37] = "0 0 -31";
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logicPortDir[37] = 5;
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logicPortUIName[37] = "Enable";
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logicPortCauseUpdate[37] = true;
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logicPortType[38] = 0;
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logicPortPos[38] = "0 0 31";
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logicPortDir[38] = 4;
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logicPortUIName[38] = "Out";
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};
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