new rom

bricks/gen/newcode/Mux 3 Bit.cs

@@ -44,67 +44,56 @@ datablock fxDtsBrickData(LogicGate_Mux3_Data){
 	logicPortPos[0] = "7 0 0";
 	logicPortDir[0] = 3;
 	logicPortUIName[0] = "Sel0";
-	logicPortCauseUpdate[0] = true;
 	
 	logicPortType[1] = 1;
 	logicPortPos[1] = "5 0 0";
 	logicPortDir[1] = 3;
 	logicPortUIName[1] = "Sel1";
-	logicPortCauseUpdate[1] = true;
 	
 	logicPortType[2] = 1;
 	logicPortPos[2] = "3 0 0";
 	logicPortDir[2] = 3;
 	logicPortUIName[2] = "Sel2";
-	logicPortCauseUpdate[2] = true;
 	
 	logicPortType[3] = 1;
 	logicPortPos[3] = "7 0 0";
 	logicPortDir[3] = 1;
 	logicPortUIName[3] = "In0";
-	logicPortCauseUpdate[3] = true;
 	
 	logicPortType[4] = 1;
 	logicPortPos[4] = "5 0 0";
 	logicPortDir[4] = 1;
 	logicPortUIName[4] = "In1";
-	logicPortCauseUpdate[4] = true;
 	
 	logicPortType[5] = 1;
 	logicPortPos[5] = "3 0 0";
 	logicPortDir[5] = 1;
 	logicPortUIName[5] = "In2";
-	logicPortCauseUpdate[5] = true;
 	
 	logicPortType[6] = 1;
 	logicPortPos[6] = "1 0 0";
 	logicPortDir[6] = 1;
 	logicPortUIName[6] = "In3";
-	logicPortCauseUpdate[6] = true;
 	
 	logicPortType[7] = 1;
 	logicPortPos[7] = "-1 0 0";
 	logicPortDir[7] = 1;
 	logicPortUIName[7] = "In4";
-	logicPortCauseUpdate[7] = true;
 	
 	logicPortType[8] = 1;
 	logicPortPos[8] = "-3 0 0";
 	logicPortDir[8] = 1;
 	logicPortUIName[8] = "In5";
-	logicPortCauseUpdate[8] = true;
 	
 	logicPortType[9] = 1;
 	logicPortPos[9] = "-5 0 0";
 	logicPortDir[9] = 1;
 	logicPortUIName[9] = "In6";
-	logicPortCauseUpdate[9] = true;
 	
 	logicPortType[10] = 1;
 	logicPortPos[10] = "-7 0 0";
 	logicPortDir[10] = 1;
 	logicPortUIName[10] = "In7";
-	logicPortCauseUpdate[10] = true;
 	
 	logicPortType[11] = 1;
 	logicPortPos[11] = "7 0 0";