redo/Brick_LuaLogic
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

new rom

Browse Source
This commit is contained in:
Redo
2022-10-05 15:43:07 -06:00
parent 519a887dca
commit fe8057f4ec
494 changed files with 293926 additions and 2323 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
bricks/gen/newcode/ROM 16x16.cs
View File

@@ -1,10 +1,10 @@
datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
datablock fxDtsBrickData(LogicGate_Rom16x16x1_Data){
brickFile = $LuaLogic::Path @ "bricks/gen/newbricks/ROM 16x16.blb";
iconName = $LuaLogic::Path @ "bricks/gen/newicons/ROM 16x16";
category = "Logic Bricks";
subCategory = "Special I/O";
subCategory = "ROM";
uiName = "ROM 16x16";
logicUIName = "ROM 16x16";
logicUIDesc = "";
@@ -61,61 +61,58 @@ datablock fxDtsBrickData(LogicGate_Rom16x16_Data){
isLogicRom = true;
logicRomY = 16;
logicRomZ = 1;
logicRomX = 16;
logicPortType[0] = 1;
logicPortPos[0] = "15 -15 0";
logicPortDir[0] = 3;
logicPortUIName[0] = "Addr0";
logicPortUIName[0] = "A0";
logicPortType[1] = 1;
logicPortPos[1] = "13 -15 0";
logicPortDir[1] = 3;
logicPortUIName[1] = "Addr1";
logicPortUIName[1] = "A1";
logicPortType[2] = 1;
logicPortPos[2] = "11 -15 0";
logicPortDir[2] = 3;
logicPortUIName[2] = "Addr2";
logicPortUIName[2] = "A2";
logicPortType[3] = 1;
logicPortPos[3] = "9 -15 0";
logicPortDir[3] = 3;
logicPortUIName[3] = "Addr3";
logicPortUIName[3] = "A3";
logicPortType[4] = 1;
logicPortPos[4] = "7 -15 0";
logicPortDir[4] = 3;
logicPortUIName[4] = "Addr4";
logicPortUIName[4] = "A4";
logicPortType[5] = 1;
logicPortPos[5] = "5 -15 0";
logicPortDir[5] = 3;
logicPortUIName[5] = "Addr5";
logicPortUIName[5] = "A5";
logicPortType[6] = 1;
logicPortPos[6] = "3 -15 0";
logicPortDir[6] = 3;
logicPortUIName[6] = "Addr6";
logicPortUIName[6] = "A6";
logicPortType[7] = 1;
logicPortPos[7] = "1 -15 0";
logicPortDir[7] = 3;
logicPortUIName[7] = "Addr7";
logicPortUIName[7] = "A7";
logicPortType[8] = 0;
logicPortPos[8] = "15 15 0";
logicPortDir[8] = 1;
logicPortUIName[8] = "Out";
logicPortUIName[8] = "O0";
logicPortType[9] = 1;
logicPortPos[9] = "15 -15 0";
logicPortDir[9] = 2;
logicPortUIName[9] = "In";
logicPortUIName[9] = "Clock";
logicPortCauseUpdate[9] = true;
};
function LogicGate_Rom16x16_Data::Logic_onAdd(%data, %brick) {
lualogic_rom_updatedata(%brick);
}