make sim use proper OOP

This commit is contained in:
Redo0
2021-05-25 14:18:13 -05:00
parent 0963ef8ca8
commit be2df1ef33
8 changed files with 74 additions and 56 deletions

View File

@@ -35,7 +35,7 @@ function Group.addwire(self, wire)
Wire.setgroup(wire, self)
Wire.update(wire)
Simulation.queuegroup(self.sim, self)
Simulation.queuegroup(Group.getsim(self), self)
end
end
end
@@ -43,35 +43,37 @@ end
function Group.removewire(self, wire)
Wire.setgroup(wire, nil)
self.wires[wire] = nil
local sim = Group.getsim(self)
for k, wire in pairs(self.wires) do
Wire.setgroup(wire, nil)
end
for k, port in pairs(self.out_ports) do
Port.setgroup(port, nil)
end
for k, port in pairs(self.in_ports) do
Port.setgroup(port, nil)
end
for k, wire in pairs(self.wires) do
Simulation.connectwire(self.sim, wire)
Simulation.connectwire(sim. wire)
end
for k, port in pairs(self.out_ports) do
Simulation.connectport(self.sim, port)
Simulation.connectport(sim, port)
end
for k, port in pairs(self.in_ports) do
Simulation.connectport(self.sim, port)
Simulation.connectport(sim, port)
end
self.wires = {}
self.out_ports = {}
self.in_ports = {}
self.nwires = 0
self.nout_ports = 0
self.nin_ports = 0
@@ -83,7 +85,7 @@ function Group.addport(self, port)
if port.type == PortTypes.output then
self.out_ports[port] = port
self.nout_ports = self.nout_ports + 1
self.sim:queuegroup(self)
Simulation.queuegroup(Group.getsim(self), self)
elseif port.type == PortTypes.input then
self.in_ports[port] = port
self.nin_ports = self.nin_ports + 1
@@ -100,11 +102,11 @@ function Group.removeport(self, port)
self.nin_ports = self.nin_ports - 1
end
Simulation.queuegroup(self.sim, self)
Simulation.queuegroup(Group.getsim(self), self)
end
function Group.mergewith(self, group)
if self:getsize() >= group:getsize() then
if Group.getsize(self) >= Group.getsize(group) then
Group.mergeinto(group, self)
return self
else
@@ -139,12 +141,16 @@ end
function Group.setstate(self, state)
if state ~= self.state then
self.state = state
self.updatetick = self.sim.currenttick
self.updatetick = Group.getsim(self).currenttick
for k, port in pairs(self.in_ports) do
Port.setinputstate(port, state)
end
Simulation.queuegroupfx(self.sim, self)
Simulation.queuegroupfx(Group.getsim(self), self)
end
end
function Group.getsim(group)
return group.sim
end